Scalable Resonant Power Clock Generation for Adiabatic Logic Design. - Ragh Kuttappa; Leo Filippini; Nicholas Sica; Baris Taskin (ISVLSI, 2021)

High-Speed Phase-Based Computing. - Nicholas Sica; Ragh Kuttappa; Vinayak Honkote; Baris Taskin (ISCAS, 2024)