Testing of Bit-Serial Signal Processors. - Nick Kanopoulos; G. Thomas Mitchell (ITC, 1983)

Design for Testability and Self-Testing Approaches for Bit-Serial signal Processors. - Nikos Kanopoulos; G. Thomas Mitchell (IEEE Des. Test, 1984)

A single-chip adaptive delta modulator with optimum performance. - Nick Kanopoulos; Vassilios Makios (Integr., 1985)

A High-Performance Single-Chip VLSI Signal Processor Architecture. - Nick Kanopoulos; Peter N. Marinos (Aegean Workshop on Computing, 1986)

A monolithic scan-line bit producer for real-time image rasterization. - Nick Kanopoulos; Nagesh Vasanthavada (Microprocess. Microprogramming, 1987)

CAD Tools for Supporting System Design for Testability. - Jill J. Hallenbeck; Nick Kanopoulos; Nagesh Vasanthavada; James W. Watterson (ITC, 1988)

Design of a bus-monitor for real-time applications. - Nick Kanopoulos; Peter N. Marinos (Microprocess. Microprogramming, 1988)

Design of an image edge detection filter using the Sobel operator. - Nick Kanopoulos; Nagesh Vasanthavada; Robert L. Baker 003 (IEEE J. Solid State Circuits, 1988)

The Test Engineer's Assistant: A Support Environment for Hardware Design for Testability. - Jill J. Hallenbeck; James R. Cybrynski; Nick Kanopoulos; Tassos Markas; Nagesh Vasanthavada (Computer, 1989)

A built-in test module for fault isolation. - Nagesh Vasanthavada; Nick Kanopoulos (IEEE Des. Test, 1989)

On the design of a real-time digital median filter. - J. Dodrill; Nick Kanopoulos (Microprocessing and Microprogramming, 1989)

Creating the IC palette [ASIC design]. - Mark Royals; Tassos Markas; Tianmaw Yang; Nick Kanopoulos (RSP, 1990)

On Distributed Fault Simulation. - Tassos Markas; Mark Royals; Nick Kanopoulos (Computer, 1990)

A bus-monitor unit for fault-tolerant system configurations. - Tassos Markas; Nick Kanopoulos (Microprocessing and Microprogramming, 1990)

Testing of differential cascade voltage switch (DCVS) circuits. - Nick Kanopoulos; Nagesh Vasanthavada (IEEE J. Solid State Circuits, 1990)

The split boundary scan register technique for testing board interconnects. - Nazar S. Haider; Nick Kanopoulos (VTS, 1992)

A new serial/parallel two's complement multiplier for vlsi digital signal processing. - George Alexiou; Nick Kanopoulos (Int. J. Circuit Theory Appl., 1992)

Design and implementation of a totally self-checking 16 × 16 bit array multiplier. - Nick Kanopoulos; Joseph H. Carabetta (Integr., 1992)

A user programmable macrocell generator for the IEEE 1149.1 boundary scan standard interface port. - Mark Royals; Tassos Markas; Nick Kanopoulos (Microprocess. Microprogramming, 1992)

Design of Self-Checking Circuits Using DCVS Logic: A Case Study. - Nick Kanopoulos; Dimitris Pantzartzis; Frederick R. Bartram (IEEE Trans. Computers, 1992)

Efficient board interconnect testing using the split boundary scan register. - Nazar S. Haider; Nick Kanopoulos (J. Electron. Test., 1993)

On the design and implementation of a lossless data compression and decompression chip. - Mark Royals; Tassos Markas; Nick Kanopoulos; John H. Reif; James A. Storer (IEEE J. Solid State Circuits, 1993)

Design and Implementation of a High-Performance, Modular, Sorting Engine. - George Alexiou; Dimitrios Stiliadis; Nick Kanopoulos (EDAC-ETC-EUROASIC, 1994)

On the design of a high-performance, expandable, sorting engine. - George Alexiou; Dimitrios Stiliadis; Nick Kanopoulos (Integr., 1994)

Multiple boundary scan-paths for minimizing circuit-board test-application time. - Theodoros Antonakopoulos 001; Nick Kanopoulos (Microprocess. Microprogramming, 1994)

Design and DCVS implementation of a self-checking bus-monitor unit for highly reliable fault-tolerant system configurations. - Tassos Markas; Mark Royals; Nick Kanopoulos (IEEE Trans. Very Large Scale Integr. Syst., 1994)

Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits. - Jason P. Hurst; Nick Kanopoulos (Asian Test Symposium, 1995)

Optimal synthesis of differential cascode voltage switch (DCVS) logic circuits using ordered binary decision diagrams (OBDDs). - Theodore Karoubalis; George Alexiou; Nick Kanopoulos (EURO-DAC, 1995)

Reducing the Time to Market Through Rapid Prototyping - Guest Editors' Introduction. - Apostolos Dollas; Nick Kanopoulos (Computer, 1995)

A new efficient dcvs circuit synthesis technique used for an improved implementation of a serial/parallel multiplier. - Theodore Karoubalis; Kostas Adaos; George Alexiou; Nick Kanopoulos (Int. J. Circuit Theory Appl., 1995)

A versatile wireless system for real-time telemetry applications. - Theodoros Antonakopoulos 001; C. Powers; Nick Kanopoulos (ICECS, 1996)

Automatic synthesis of an 8-bit CPU with 100% on-line error detection capability. - Tassos Markas; E. Edwards; S. Wang; J. Medero; Nick Kanopoulos (ICECS, 1996)

TESPAD: a testability specifications advisor for a structured test methodology. - W. Weber; Michael G. McNamer; Nick Kanopoulos (ICECS, 1996)

An Extensible, Low Cost Rapid Prototyping Environment Based on a Reconfigurable Set of FPGAs. - Kostas Adaos; George Alexiou; Nick Kanopoulos (International Workshop on Rapid System Prototyping, 1998)

A dual rail circuits synthesis environment for the implementation of multiple output boolean functions. - Theodore Karoubalis; George Alexiou; Nick Kanopoulos (Int. J. Circuit Theory Appl., 1998)

Efficient implementation of a serial/parallel multiplier for IP based development and rapid prototyping in VLSI digital signal processing. - Kostas Adaos; G. Ph. Alexiou; Nikos Kanopoulos (ICECS, 1999)

Testability Concepts and DFT. - Nick Kanopoulos (The VLSI Handbook, 1999)

Development of reusable serial FIR filters with reprogrammable coefficients designed for serial dataflow architectures. - Kostas Adaos; George Alexiou; Nick Kanopoulos (ICECS, 2000)

Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization. - Nick Kanopoulos (PATMOS, 2004)