E1 Ultimate Limits of Integrated Electronics. - Nicky Lu; C. K. Wang; Philip Wong; Sreedhar Natarajan (ISSCC, 2007)

Private Equity: Fight them or Invite them. - Sreedhar Natarajan; Nicky Lu (ISSCC, 2008)

Introduction to the Special Section on the 2007 Asian Solid-State Circuits Conference (A-SSCC'07). - Nicky Lu; Shyh-Jye Jou (IEEE J. Solid State Circuits, 2008)

Future system and memory architectures: Transformations by technology and applications. - Nicky Lu; Leland Chang; Daisaburo Takashima (ISSCC, 2011)

A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. - Pei-Wen Luo; Chi-Kang Chen; Yu-Hui Sung; Wei Wu 024; Hsiu-Chuan Shih; Chia-Hsin Lee; Kuo-Hua Lee; Ming-Wei Li; Mei-Chiang Lung; Chun-Nan Lu; Yung-Fa Chou; Po-Lin Shih; et al. (VLSIC, 2015)

A 4.8GB/s 256Mb(x16) Reduced-Pin-Count DRAM and Controller Architecture (RPCA) to Reduce Form-Factor & Cost for IOT/Wearable/TCON/Video/AI-Edge Systems. - Chun Shiah; C. N. Chang; Richard Crisp; C. P. Lin; C. N. Pan; C. P. Chuang; H. L. Chen; S. H. Jheng; T. F. Chang; W. J. Huang; K. C. Ting; Rick Dai; et al. (VLSI Circuits, 2019)

Optimizing Monolithic and Heterogeneous Integration to Create Intelligent-Grand-Scale-Integration for Smart MicroSystems. - Nicky Lu (DRC, 2021)

Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns. - Nicky Lu; Chun Shiah; Juang-Ying Chueh; Bor-Doou Rong; Wei-Jr Huang; Ho-Yin Chen; Cheng-Nan Chang; Chia-Wei Chang; Tzung-Shen Chen (VLSI Circuits, 2021)