Architecture and VLSI Design of a VLSI Neural Signal Processor. - Ulrich Ramacher; Jörg Beichter; Nico Brüls; Elisabeth Sicheneder (ISCAS, 1993)

Multiprocessor And Memory Architecture Of The Neurocomputer Synapse-1. - Ulrich Ramacher; Wolfgang Raab; Joachim K. Anlauf; J. A. Ulrich Hachmann; Jörg Beichter; Nico Brüls; Matthias Wesseling; Elisabeth Sicheneder; Reinhard Männer; Joachim Gläß; Andreas Wurz (Int. J. Neural Syst., 1993)

Design of a general-purpose neural signal processor. - Jörg Beichter; Nico Brüls; Elisabeth Sicheneder; Ulrich Ramacher; Heinrich Klar (Neurocomputing, 1993)

A general-purpose signal processor architecture for neurocomputing and preprocessing applications. - Ulrich Ramacher; Jörg Beichter; Nico Brüls (J. VLSI Signal Process., 1993)

SYNAPSE-1: a high-speed general purpose parallel neurocomputer system. - Ulrich Ramacher; Wolfgang Raab; J. A. Ulrich Hachmann; Jörg Beichter; Nico Brüls; Matthias Wesseling; Elisabeth Sicheneder; Joachim Gläß; Andreas Wurz; Reinhard Männer (IPPS, 1995)

A 100-GOPS Programmable Processor for Vehicle Vision Systems. - Wolfgang Raab; Nico Brüls; J. A. Ulrich Hachmann; Jens Harnisch; Ulrich Ramacher; Christian Sauer 001; Axel Techmer (IEEE Des. Test Comput., 2003)

100 GOPS vision processor for automotive applications. - Ulrich Ramacher; Nico Brüls; J. A. Ulrich Hachmann; Jens Harnisch; Wolfgang Raab; Axel Techmer (SIGARCH Comput. Archit. News, 2003)

Architecture and implementation of a Software-Defined Radio baseband processor. - Ulrich Ramacher; Wolfgang Raab; J. A. Ulrich Hachmann; Dominik Langen; Jörg Berthold; R. Kramer; A. Schackow; Cyprian Grassmann; Mirko Sauermann; P. Szreder; F. Capar; G. Obradovic; et al. (ISCAS, 2011)