BIST Based Interconnect Fault Location for FPGAs. - Nicola Campregher; Peter Y. K. Cheung; Milan Vasilko (FPL, 2004)

Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. - Nicola Campregher; Peter Y. K. Cheung; George A. Constantinides; Milan Vasilko (FPGA, 2005)

FPGA Interconnect Fault tolerance. - Nicola Campregher (FPL, 2005)

Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes. - Nicola Campregher; Peter Y. K. Cheung; George A. Constantinides; Milan Vasilko (FPL, 2005)

Yield enhancements of design-specific FPGAs. - Nicola Campregher; Peter Y. K. Cheung; George A. Constantinides; Milan Vasilko (FPGA, 2006)

Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. - Nicola Campregher; Peter Y. K. Cheung; George A. Constantinides; Milan Vasilko (FPL, 2006)