A fully integrated 2.4-GHz LC-VCO frequency synthesizer with 3-ps jitter in 0.18-μm standard digital CMOS copper technology. - Nicola Da Dalt; Sven Derksen; Patrizia Greco; Christoph Sandner; Harald Schmid; Klaus Strohmayer (IEEE J. Solid State Circuits, 2002)

A subpicosecond jitter PLL for clock generation in 0.12-μm digital CMOS. - Nicola Da Dalt; Christoph Sandner (IEEE J. Solid State Circuits, 2003)

A low jitter triple-band digital LC PLL in 130nm CMOS. - Nicola Da Dalt; Edwin Thaller; Peter Gregorius; Lajos Gazsi (ESSCIRC, 2004)

Effect of jitter on asynchronous sampling with finite number of samples. - Nicola Da Dalt (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS. - Nicola Da Dalt; Edwin Thaller; Peter Gregorius; Lajos Gazsi (IEEE J. Solid State Circuits, 2005)

Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture. - Roberto Nonis; Nicola Da Dalt; Pierpaolo Palestri; Luca Selmi (IEEE J. Solid State Circuits, 2005)

A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs. - Nicola Da Dalt (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A 10b 10GHz digitlly controlled LC oscillator in 65nm CMOS. - Nicola Da Dalt; Claus Kropf; Markus Burian; Thomas Hartig; Hermann Eul (ISSCC, 2006)

Markov Chains-Based Derivation of the Phase Detector Gain in Bang-Bang PLLs. - Nicola Da Dalt (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs. - Luca Bizjak; Nicola Da Dalt; Peter Thurner; Roberto Nonis; Pierpaolo Palestri; Luca Selmi (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation. - Nicola Da Dalt (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS. - Stefano Dal Toso; Andrea Bevilacqua; Marc Tiebout; Nicola Da Dalt; Andrea Gerosa; Andrea Neviani (ESSCIRC, 2009)

A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming. - Stefan Mendel; Christian Vogel 001; Nicola Da Dalt (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A 4.1 to 5.1 GHz 430 μA injection-locked frequency divider by 7 in 65 nm CMOS. - Andrea Bevilacqua; Leonardo Lorenzon; Nicola Da Dalt; Andrea Gerosa; Andrea Neviani (ESSCIRC, 2010)

A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS. - Werner Grollitsch; Roberto Nonis; Nicola Da Dalt (ISSCC, 2010)

A 0.06 mm 2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS. - Stefano Dal Toso; Andrea Bevilacqua; Marc Tiebout; Nicola Da Dalt; Andrea Gerosa; Andrea Neviani (IEEE J. Solid State Circuits, 2010)

Jitter Noise of Sampled Multitone Signals. - Martin Clara; Nicola Da Dalt (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

ES3: High-speed communications on 4 wheels: What's in your next car? - Nicola Da Dalt; Ajith Amerasekera (ISSCC, 2013)

An all-digital PLL using random modulation for SSC generation in 65nm CMOS. - Nicola Da Dalt; Peter Pridnig; Werner Grollitsch (ISSCC, 2013)

A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider. - Roberto Nonis; Werner Grollitsch; Thomas Santa; Dmytro Cherniak; Nicola Da Dalt (ISSCC, 2013)

digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture. - Roberto Nonis; Werner Grollitsch; Thomas Santa; Dmytro Cherniak; Nicola Da Dalt (IEEE J. Solid State Circuits, 2013)

F6: Energy-efficient I/O design for next-generation systems. - Frank O'Mahony; Nicola Da Dalt; Ken Chang; Hisakatsu Yamaguchi; Chulwoo Kim; Elad Alon (ISSCC, 2014)

An Analysis of Phase Noise in Realigned VCOs. - Nicola Da Dalt (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters. - Dmytro Cherniak; Michael Aichner; Roberto Nonis; Nicola Da Dalt (ESSCIRC, 2015)

F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data. - Ken Chang; Frank O'Mahony; Elad Alon; Hyeon-Min Bae; Nicola Da Dalt; Eric Fluhr (ISSCC, 2015)

Design and implementation of switched coil LC-VCOs in the GHz range using the self-inductance technique. - Federico Cernoia; Davide Ponton; Pierpaolo Palestri; Peter Thurner; Nicola Da Dalt; Giulio Cecco; Luca Selmi (Int. J. Circuit Theory Appl., 2015)