Analysis of the ideal SFDR limit for an N bit digital-to-analog converter. - Nicola Ghittori; Andrea Vigna; Piero Malcovati (ICECS, 2005)

Design of a low-power variable gain amplifier for reconfigurable wireless receivers. - Nicola Ghittori; Andrea Vigna; Piero Malcovati; Stefano D'Amico; Andrea Baschirotto (ICECS, 2005)

Behavioral analysis and dimensioning of UMTS transmitters baseband blocks. - Nicola Ghittori; Andrea Vigna; Piero Malcovati; Stefano D'Amico; Andrea Baschirotto (ISCAS (1), 2005)

A low-distortion 1.2 V DAC+filter for transmitters in wireless applications. - Nicola Ghittori; Andrea Vigna; Piero Malcovati; Stefano D'Amico; Andrea Baschirotto (ISCAS (1), 2005)

Low-power 6-bit flash ADC for high-speed data converters architectures. - Vincenzo Ferragina; Nicola Ghittori; Franco Maloberti (ISCAS, 2006)

Analog baseband channel for GSM/UMTS/WLAN/Bluetooth reconfigurable multistandard terminals. - Nicola Ghittori; Andrea Vigna; Piero Malcovati; Stefano D'Amico; Andrea Baschirotto (ISCAS, 2006)

1.2-V Low-Power Multi-Mode DAC+Filter Blocks for Reconfigurable (WLAN/UMTS, WLAN/Bluetooth) Transmitters. - Nicola Ghittori; Andrea Vigna; Piero Malcovati; Stefano D'Amico; Andrea Baschirotto (IEEE J. Solid State Circuits, 2006)

A 1.2- V 30.4-dBm OIP3 Reconfigurable Analog Baseband Channel for UMTS/WLAN Transmitters. - Nicola Ghittori; Andrea Vigna; Piero Malcovati; Stefano D'Amico; Andrea Baschirotto (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

A 5nV/√Hz-IRN, 78dB-gain-range, 78dB-DR multi-standard baseband chain for Bluetooth, UMTS and WLAN. - Stefano D'Amico; Marcello De Matteis; Andrea Baschirotto; Nicola Ghittori; Andrea Vigna; Piero Malcovati (ESSCIRC, 2007)

A CMOS 5 nV/√Hz 74-dB-Gain-Range 82-dB-DR Multistandard Baseband Chain for Bluetooth, UMTS, and WLAN. - Stefano D'Amico; Andrea Baschirotto; Marcello De Matteis; Nicola Ghittori; Andrea Vigna; Piero Malcovati (IEEE J. Solid State Circuits, 2008)

Analysis and Measurement of Crosstalk Effects on Mixed-Signal CMOS ICs With Different Mounting Technologies. - Vincenzo Ferragina; Nicola Ghittori; Guido Torelli; Giorgio Boselli; Gabriella Trucco; Valentino Liberali (IEEE Trans. Instrum. Meas., 2010)

27.8 A 0.076mm2 12b 26.5mW 600MS/s 4×-interleaved subranging SAR-ΔΣ ADC with on-chip buffer in 28nm CMOS. - Alessandro Venca; Nicola Ghittori; Alessandro Bosi; Claudio Nani (ISSCC, 2016)

A 0.076 mm2 12 b 26.5 mW 600 MS/s 4-Way Interleaved Subranging SAR-ΔΣ ADC With On-Chip Buffer in 28 nm CMOS. - Alessandro Venca; Nicola Ghittori; Alessandro Bosi; Claudio Nani (IEEE J. Solid State Circuits, 2016)

A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET. - Matteo Pisati; Fernando De Bernardinis; Paolo Pascale; Claudio Nani; Marco Sosio; Enrico Pozzati; Nicola Ghittori; Federico Magni; Marco Garampazzi; Giacomino Bollati; Antonio Milani; Alberto Minuti; et al. (ISSCC, 2019)

A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET. - Matteo Pisati; Alberto Minuti; Giacomino Bollati; Fabio Giunco; Roberto G. Massolini; Giovanni Cesura; Fernando De Bernardinis; Paolo Pascale; Claudio Nani; Nicola Ghittori; Enrico Pozzati; Marco Sosio; et al. (IEEE J. Solid State Circuits, 2020)

A 800Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5nm FinFet Process. - Fabio Giunco; Marco Sosio; Claudio Nani; Ivan Fabiano; Travis Lovitt; Victor Karam; D. Albano; C. Asero; Nicola Codega; Marco Garampazzi; Nicola Ghittori; D. Herbas; et al. (VLSI Technology and Circuits, 2024)

A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz. - Claudio Nani; Enrico Monaco; Nicola Ghittori; Alessandro Bosi; Domenico Albano; Claudio Asero; Nicola Codega; Alessio Di Pasquo; Ivan Fabiano; Marco Garampazzi; Fabio Giunco; Leonardo Daniel Herbas Burgos; et al. (VLSI Technology and Circuits, 2024)

An Eight-Lane 800-Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5-nm FinFET Process. - Fabio Giunco; Marco Sosio; Claudio Nani; Ivan Fabiano; Travis Lovitt; Victor Karam; Domenico Albano; Claudio Asero; Nicola Codega; Marco Garampazzi; Nicola Ghittori; Leonardo Daniel Herbas Burgos; et al. (IEEE J. Solid State Circuits, 2025)

A 5-nm 60-GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 35.2dB SNDR up to 32 GHz. - Claudio Nani; Enrico Monaco; Nicola Ghittori; Alessandro Bosi; Domenico Albano; Claudio Asero; Nicola Codega; Alessio Di Pasquo; Ivan Fabiano; Marco Garampazzi; Fabio Giunco; Leonardo Daniel Herbas Burgos; et al. (IEEE J. Solid State Circuits, 2025)