Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling. - Patrick Sittel; Nicolai Fiege; Martin Kumm; Peter Zipf (ReConFig, 2019)

Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling. - Nicolai Fiege; Patrick Sittel; Peter Zipf (FCCM, 2022)

Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis. - Nicolai Fiege; Patrick Sittel; Peter Zipf (FPL, 2022)

Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals. - Nicolai Fiege; Patrick Sittel; Peter Zipf (FPL, 2022)

Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis. - Patrick Sittel; Nicolai Fiege; John Wickerson; Peter Zipf (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining. - Nicolai Fiege; Peter Zipf (ACM Trans. Reconfigurable Technol. Syst., 2023)

Bit-Level Optimized Constant Multiplication Using Boolean Satisfiability. - Nicolai Fiege; Martin Kumm; Peter Zipf (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Fantastic Circuits and Where to Find Them - A Holistic ILP Formulation for Model-Based Hardware Design. - Nicolai Fiege; Peter Zipf (ACM Trans. Reconfigurable Technol. Syst., 2025)