The gem5 Simulator: Version 20.0+. - Jason Lowe-Power; Abdul Mutaal Ahmad; Ayaz Akram; Mohammad Alian; Rico Amslinger; Matteo Andreozzi; Adrià Armejach; Nils Asmussen; Srikant Bharadwaj; Gabe Black; Gedare Bloom; Bobby R. Bruce; et al. (CoRR, 2020)

From micro-OPs to abstract resources: constructing a simpler CPU performance model through microbenchmarking. - Nicolas Derumigny; Fabian Gruber; Théophile Bastian; Christophe Guillon; Louis-Noël Pouchet; Fabrice Rastello (CoRR, 2020)

PALMED: Throughput Characterization for Superscalar Architectures. - Nicolas Derumigny; Théophile Bastian; Fabian Gruber; Guillaume Iooss; Christophe Guillon; Louis-Noël Pouchet; Fabrice Rastello (CGO, 2022)

Automatic generation of performance model for heterogeneous architectures. (Génération automatique de modèles de performance pour architectures hétérogènes). - Nicolas Derumigny (2023)

Userland Page Table - A Key for Transparent Persistent Memory. - Jana Toljaga; Nicolas Derumigny; Yohan Pipereau; Mathieu Bacou; Gaël Thomas 001 (Middleware Demos/Posters/Doctoral Symposium, 2024)

An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators. - Corentin Ferry; Nicolas Derumigny; Steven Derrien; Sanjay V. Rajopadhye (CoRR, 2024)

Performance bottlenecks detection through microarchitectural sensitivity. - Hugo Pompougnac; Alban Dutilleul; Christophe Guillon; Nicolas Derumigny; Fabrice Rastello (CoRR, 2024)

Performance Debugging through Microarchitectural Sensitivity and Causality Analysis. - Alban Dutilleul; Hugo Pompougnac; Nicolas Derumigny; Gabriel Rodriguez; Valentin Trophime; Christophe Guillon; Fabrice Rastello (CoRR, 2024)