The vector fixed point unit of the synergistic processor element of the cell architecture processor. - Nicolas Mäding; Jens Leenstra; Jürgen Pille; Rolf Sautter; Stefan Büttner; Sebastian Ehrenreich; W. Haller (ESSCIRC, 2005)

BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. - Christian G. Zoellin; Hans-Joachim Wunderlich; Nicolas Mäding; Jens Leenstra (ITC, 2006)

Scan Test Planning for Power Reduction. - Michael E. Imhof; Christian G. Zoellin; Hans-Joachim Wunderlich; Nicolas Mäding; Jens Leenstra (DAC, 2007)

IBM POWER6 accelerators: VMX and DFU. - Lee Eisen; John Wesley Ward III; Hans-Werner Tast; Nicolas Mäding; Jens Leenstra; Silvia M. Müller; Christian Jacobi 002; Jochen Preiss; Eric M. Schwarz; Steven R. Carlough (IBM J. Res. Dev., 2007)

Scan chain clustering for test power reduction. - Melanie Elm; Hans-Joachim Wunderlich; Michael E. Imhof; Christian G. Zoellin; Jens Leenstra; Nicolas Mäding (DAC, 2008)