A Hierarchical Track and Hold Circuit for High Speed ADC-Based Receivers in 22nm FDSOI. - David Cordova; Wim Cops; Yann Deval; Francois Rivet; Hervé Lapuyade; Nicolas Nodenot; Yohan Piccin (ICECS, 2019)

A 0.8V 875 MS/s 7b low-power SAR ADC for ADC-Based Wireline Receivers in 22nm FDSOI. - David Cordova; Wim Cops; Yann Deval; Francois Rivet; Hervé Lapuyade; Nicolas Nodenot; Yohan Piccin (VLSI-SOC, 2020)

Low-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22 nm FDSOI. - David Cordova; Wim Cops; Yann Deval; François Rivet; Hervé Lapuyade; Nicolas Nodenot; Yohan Piccin (VLSI-SoC (Selected Papers), 2020)

Optimized body-biasing calibration methodology for high-speed comparators in 22nm FDX. - David Cordova; Wim Cops; Yann Deval; Francois Rivet; Hervé Lapuyade; Nicolas Nodenot; Yohan Piccin (LASCAS, 2021)

Design methodology for 112Gb/s PAM4 Wireline ADC-Based Receivers. - David Cordova; Wim Cops; Yann Deval; Francois Rivet; Hervé Lapuyade; Nicolas Nodenot; Yohan Piccin (LASCAS, 2021)