Practical Setup Time Violation Attacks on AES. - Nidhal Selmane; Sylvain Guilley; Jean-Luc Danger (EDCC, 2008)

Silicon-level Solutions to Counteract Passive and Active Attacks. - Sylvain Guilley; Laurent Sauvage; Jean-Luc Danger; Nidhal Selmane; Renaud Pacalet (FDTC, 2008)

Fault Analysis Attack on an FPGA AES Implementation. - Farouk Khelil; Mohamed Hamdi; Sylvain Guilley; Jean-Luc Danger; Nidhal Selmane (NTMS, 2008)

WDDL is Protected against Setup Time Violation Attacks. - Nidhal Selmane; Shivam Bhasin; Sylvain Guilley; Tarik Graba; Jean-Luc Danger (FDTC, 2009)

Security Evaluation of Different AES Implementations Against Practical Setup Time Violation Attacks in FPGAs. - Shivam Bhasin; Jean-Luc Danger; Sylvain Guilley; Nidhal Selmane (HOST, 2009)

Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. - Shivam Bhasin; Jean-Luc Danger; Florent Flament; Tarik Graba; Sylvain Guilley; Yves Mathieu; Maxime Nassar; Laurent Sauvage; Nidhal Selmane (ReConFig, 2009)

Countering early evaluation: an approach towards robust dual-rail precharge logic. - Shivam Bhasin; Sylvain Guilley; Florent Flament; Nidhal Selmane; Jean-Luc Danger (WESS, 2010)

Fault Injection Resilience. - Sylvain Guilley; Laurent Sauvage; Jean-Luc Danger; Nidhal Selmane (FDTC, 2010)

Global and local Fault attacks on AES cryptoprocessor : Implementation and Countermeasures. (Attaques en fautes globales et locales sur les cryptoprocesseurs AES : mise en œuvre et contremesures). - Nidhal Selmane (2010)

Performance evaluation of protocols resilient to physical attacks. - Sylvain Guilley; Laurent Sauvage; Jean-Luc Danger; Nidhal Selmane; Denis Réal (HOST, 2011)

Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks. - Nidhal Selmane; Shivam Bhasin; Sylvain Guilley; Jean-Luc Danger (IET Inf. Secur., 2011)