A STAFAN-like functional testability measure for register-level circuits. - C. P. Ravikumar; Gurjeet S. Saund; Nidhi Agrawal (Asian Test Symposium, 1995)

Efficient Delay Test Generation for Modular Circuits. - Nidhi Agrawal; Parul Agarwal; C. P. Ravikumar (Great Lakes Symposium on VLSI, 1996)

Fault-tolerant routing in multiply twisted cube topology. - Nidhi Agrawal; C. P. Ravikumar (J. Syst. Archit., 1996)

An Euler Path Based Technique for Deadlock-free Multicasting. - Nidhi Agrawal; C. P. Ravikumar (ICPP, 1997)

Adaptive Routing Based on Deadlock Recovery. - Nidhi Agrawal; C. P. Ravikumar (Euro-Par, 1998)

A functional-level testability measure for register-level circuits and its estimation. - C. P. Ravikumar; Gurjeet S. Saund; Nidhi Agrawal (Microprocess. Microsystems, 1999)

Error in mathematical modelling and enhancement of sensing performance of electrostrictive capacitive sensors. - Om Prakash Thakur; Nidhi Agrawal (ICST, 2013)

Understanding clinical and non-clinical decisions under uncertainty: a scenario-based survey. - Vlad V. Simianu; Margaret A. Grounds; Susan L. Joslyn; Jared E. LeClerc; Anne P. Ehlers; Nidhi Agrawal; Rafael Alfonso-Cristancho; Abraham D. Flaxman; David R. Flum (BMC Medical Informatics Decis. Mak., 2016)

Automated Socket Anomaly Detection through Deep Learning. - Nidhi Agrawal; Min-Jian Yang; Constantinos Xanthopoulos; Vijayakumar Thangamariappan; Joe Xiao; Chee-Wah Ho; Keith Schaub; Ira Leventhal (ITC, 2020)

Improvements in Automated IC Socket Pin Defect Detection. - Vijayakumar Thangamariappan; Nidhi Agrawal; Jason Kim 008; Constantinos Xanthopoulos; Ken Butler; Ira Leventhal; Joe Xiao (ITC, 2022)