MU6V: A Parallel Vector Processing System. - Roland N. Ibbett; P. C. Capon; Nigel P. Topham (ISCA, 1985)

Context flow: An alternative to conventional pipelined architectures. - Nigel P. Topham; Amos Omondi; Roland N. Ibbett (J. Supercomput., 1988)

On the design and performance of conventional pipelined architectures. - Nigel P. Topham; Amos Omondi; Roland N. Ibbett (J. Supercomput., 1988)

A general bound on schedule length for independent tasks. - Sathiamoorthy Manoharan; Nigel P. Topham (Parallel Comput., 1990)

A Comparison of Two Memory Models for High Performance Computers. - Peter L. Bird; Nigel P. Topham; Sathiamoorthy Manoharan (CONPAR, 1992)

The Effectiveness of Decoupling. - Peter L. Bird; Alasdair Rawsthorne; Nigel P. Topham (International Conference on Supercomputing, 1993)

Performance of Weak Consistency Schemes on the DEC Alpha. - T. Harris; Nigel P. Topham (PARCO, 1993)

The Performance of Parallel Loops on SCI-Based Memory Hierarchies. - Roberto A. Hexsel; Nigel P. Topham (PARCO, 1993)

Trace-Driven Simulation of Decoupled Architectures. - Sathiamoorthy Manoharan; Nigel P. Topham; A. W. R. Crawford (HICSS (1), 1994)

Performance of the decoupled ACRI-1 architecture: the perfect club. - Nigel P. Topham; Kenneth McDougall (HPCN Europe, 1995)

Compiling and Optimizing for Decoupled Architectures. - Nigel P. Topham; Alasdair Rawsthorne; Callum McLean; Muriel Mewissen; Peter L. Bird (SC, 1995)

An Assessment of Assignment Schemes for Dependency Graphs. - Sathiamoorthy Manoharan; Nigel P. Topham (Parallel Comput., 1995)

Allocating Lifetimes to Queues in Software Pipelined Architectures. - Marcio Merino Fernandes; Josep Llosa; Nigel P. Topham (Euro-Par, 1997)

A Limitation Study into Access Decoupling. - Graham P. Jones; Nigel P. Topham (Euro-Par, 1997)

Eliminating Cache Conflict Misses through XOR-Based Placement Functions. - Antonio González 001; Mateo Valero; Nigel P. Topham; Joan-Manuel Parcerisa (International Conference on Supercomputing, 1997)

A Comparison of Data Prefetching on an Access Decoupled and Superscalar Machine. - Graham P. Jones; Nigel P. Topham (MICRO, 1997)

The Design and Performance of a Conflict-Avoiding Cache. - Nigel P. Topham; Antonio González 001; José González 002 (MICRO, 1997)

The Effect of Restricted Instruction Issue Width on an Access Decoupled Architecture. - Graham P. Jones; Nigel P. Topham (PARCO, 1997)

Partitioned Schedules for Clustered VLIW Architectures. - Marcio Merino Fernandes; Josep Llosa; Nigel P. Topham (IPPS/SPDP, 1998)

Experiencing quantitative computer architecture. - Nigel P. Topham (WCAE@ISCA, 1998)

Distributed Modulo Scheduling. - Marcio Merino Fernandes; Josep Llosa; Nigel P. Topham (HPCA, 1999)

Randomized Cache Placement for Eliminating Conflicts. - Nigel P. Topham; Antonio González 001 (IEEE Trans. Computers, 1999)

Multiple-banked register file architectures. - José-Lorenzo Cruz; Antonio González 001; Mateo Valero; Nigel P. Topham (ISCA, 2000)

OneDSP: A unifying DSP architecture for Systems-on-a-Chip. - Kar-Lik Wong; Nigel P. Topham (ICASSP, 2002)

High performance IDCT realization using complex arithmetic. - Kar-Lik Wong; Nigel P. Topham (ICASSP (2), 2003)

Synthetic Trace-Driven Simulation of Cache Memory. - Rahman Hassan; Antony Harris; Nigel P. Topham; Aristides Efthymiou (AINA Workshops (1), 2007)

Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration of embedded systems. - Richard Vincent Bennett; Alastair Colin Murray; Björn Franke; Nigel P. Topham (LCTES, 2007)

Resource Sharing in Custom Instruction Set Extensions. - Marcela Zuluaga; Nigel P. Topham (SASP, 2008)

High Speed CPU Simulation Using LTU Dynamic Binary Translation. - Daniel Jones 005; Nigel P. Topham (HiPEAC, 2009)

Introducing control-flow inclusion to support pipelining in custom instruction set extensions. - Marcela Zuluaga; Theo Kluter; Philip Brisk; Nigel P. Topham; Paolo Ienne (SASP, 2009)

Design-Space Exploration of Resource-Sharing Solutions for Custom Instruction Set Extensions. - Marcela Zuluaga; Nigel P. Topham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Code transformation and instruction set extension. - Alastair Colin Murray; Richard Vincent Bennett; Björn Franke; Nigel P. Topham (ACM Trans. Embed. Comput. Syst., 2009)

Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator. - Igor Böhm; Björn Franke; Nigel P. Topham (ICSAMOS, 2010)

Exploring the unified design-space of custom-instruction selection and resource sharing. - Marcela Zuluaga; Nigel P. Topham (ICSAMOS, 2010)

A Learning-Based Approach to the Automated Design of MPSoC Networks. - Oscar Almer; Nigel P. Topham; Björn Franke (ARCS, 2011)

A reconfigurable cache architecture for energy efficiency. - Karthik T. Sundararajan; Timothy M. Jones 001; Nigel P. Topham (Conf. Computing Frontiers, 2011)

Virtual Manycore platforms: Moving towards 100+ processor cores. - Rainer Leupers; Lieven Eeckhout; Grant Martin; Frank Schirrmeister; Nigel P. Topham; Xiaotao Chen (DATE, 2011)

Selecting the optimal system: automated design of application-specific systems-on-chip. - Oscar Almer; Miles Gould; Björn Franke; Nigel P. Topham (NoCArc@MICRO, 2011)

Generalized just-in-time trace compilation using a parallel task farm in a dynamic binary translator. - Igor Böhm; Tobias J. K. Edler von Koch; Stephen C. Kyle; Björn Franke; Nigel P. Topham (PLDI, 2011)

Scalable multi-core simulation using parallel dynamic binary translation. - Oscar Almer; Igor Böhm; Tobias J. K. Edler von Koch; Björn Franke; Stephen C. Kyle; Volker Seeker; Christopher Thompson 001; Nigel P. Topham (ICSAMOS, 2011)

Smart cache: A self adaptive cache architecture for energy efficiency. - Karthik T. Sundararajan; Timothy M. Jones 001; Nigel P. Topham (ICSAMOS, 2011)

Energy-efficient cache partitioning for future CMPs. - Karthik T. Sundararajan; Timothy M. Jones 001; Nigel P. Topham (PACT, 2012)

Design Space Exploration of Hybrid Ultra Low Power Branch Predictors. - Matthew Bielby; Miles Gould; Nigel P. Topham (ARCS, 2012)

Predicting best design trade-offs: A case study in processor customization. - Marcela Zuluaga; Edwin V. Bonilla; Nigel P. Topham (DATE, 2012)

Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs. - Karthik T. Sundararajan; Vasileios Porpodas; Timothy M. Jones 001; Nigel P. Topham; Björn Franke (HPCA, 2012)

Efficiently parallelizing instruction set simulation of embedded multi-core processors using region-based just-in-time dynamic binary translation. - Stephen C. Kyle; Igor Böhm; Björn Franke; Hugh Leather; Nigel P. Topham (LCTES, 2012)

Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description. - Harry Wagstaff; Miles Gould; Björn Franke; Nigel P. Topham (DAC, 2013)

RECAP: Region-Aware Cache Partitioning. - Karthik T. Sundararajan; Timothy M. Jones 001; Nigel P. Topham (ICCD, 2013)

High speed cycle approximate simulation for cache-incoherent MPSoCs. - Christopher Thompson 001; Miles Gould; Nigel P. Topham (ICSAMOS, 2013)

A Parallel Dynamic Binary Translator for Efficient Multi-Core Simulation. - Oscar Almer; Igor Böhm; Tobias J. K. Edler von Koch; Björn Franke; Stephen C. Kyle; Volker Seeker; Christopher Thompson 001; Nigel P. Topham (Int. J. Parallel Program., 2013)

The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation. - Karthik T. Sundararajan; Timothy M. Jones 001; Nigel P. Topham (Int. J. Parallel Program., 2013)

Efficient code generation in a region-based dynamic binary translator. - Tom Spink; Harry Wagstaff; Björn Franke; Nigel P. Topham (LCTES, 2014)

Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM. - Luigi Nardi; Bruno Bodin; M. Zeeshan Zia; John Mawer; Andy Nisbet; Paul H. J. Kelly; Andrew J. Davison; Mikel Luján; Michael F. P. O'Boyle; Graham D. Riley; Nigel P. Topham; Stephen B. Furber (ICRA, 2015)

Efficient dual-ISA support in a retargetable, asynchronous Dynamic Binary Translator. - Tom Spink; Harry Wagstaff; Björn Franke; Nigel P. Topham (SAMOS, 2015)

Characterizing memory bottlenecks in GPGPU workloads. - Saumay Dublish; Vijay Nagarajan; Nigel P. Topham (IISWC, 2016)

Cooperative Caching for GPUs. - Saumay Dublish; Vijay Nagarajan; Nigel P. Topham (ACM Trans. Archit. Code Optim., 2016)

Evaluating and mitigating bandwidth bottlenecks across the memory hierarchy in GPUs. - Saumay Dublish; Vijay Nagarajan; Nigel P. Topham (ISPASS, 2017)

High Speed Cycle-Approximate Simulation of Embedded Cache-Incoherent and Coherent Chip-Multiprocessors. - Christopher Thompson 001; Miles Gould; Nigel P. Topham (Int. J. Parallel Program., 2018)

Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs Using Machine Learning. - Saumay Dublish; Vijay Nagarajan; Nigel P. Topham (HPCA, 2019)

Mitigating JIT compilation latency in virtual execution environments. - Martin Kristien; Tom Spink; Harry Wagstaff; Björn Franke; Igor Böhm; Nigel P. Topham (VEE, 2019)

Fast and Correct Load-Link/Store-Conditional Instruction Handling in DBT Systems. - Martin Kristien; Tom Spink; Brian Campbell 001; Susmit Sarkar; Ian Stark; Björn Franke; Igor Böhm; Nigel P. Topham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Trustworthy computing on untrustworthy and Trojan-infected on-chip interconnects. - Heba Salem; Nigel P. Topham (ETS, 2021)

Detecting denial-of-service hardware Trojans in DRAM-based memory systems. - Heba Salem; Nigel P. Topham (ICECS, 2021)

Run-time integrity monitoring of untrustworthy analog front-ends. - Heba Salem; Nigel P. Topham (DATE, 2023)

Integrating HW/SW Functionality for Flexible Wireless Radio. - Alexander Strachan; Nigel P. Topham (CoRR, 2024)