An efficient technique to select logic nodes for single event transient pulse-width reduction. - Nihaar N. Mahatme; Indranil Chatterjee; Akash Patki; Daniel B. Limbrick; Bharat L. Bhuva; Ronald D. Schrimpf; William H. Robinson (Microelectron. Reliab., 2013)

Terrestrial SER characterization for nanoscale technologies: A comparative study. - Nihaar N. Mahatme; Bharat L. Bhuva; Nelson J. Gaspard; T. Assis; Y. Xu; P. Marcoux; M. Vilchis; Balaji Narasimham; A. Shih; Shi-Jie Wen; Rick Wong; N. Tam; et al. (IRPS, 2015)

Design of aging aware 5 Gbps LVDS transmitter for automotive applications. - Srikanth Jagannathan; Kumar Abhishek; Nihaar N. Mahatme; Ender Yilmaz (IRPS, 2018)

Evaluation on flip-flop physical unclonable functions in a 14/16-nm bulk FinFET technology. - H. Zhang; H. Jiang; M. R. Eaker; Kurt J. Lezon; Balaji Narasimham; Nihaar N. Mahatme; Lloyd W. Massengill; Bharat L. Bhuva (IRPS, 2018)