Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse. - Jinwoo Kim; Gauthaman Murali; Heechun Park; Eric Qin 001; Hyoukjun Kwon; Venkata Chaitanya Krishna Chekuri; Nihar Dasari; Arvind Singh; Minah Lee; Hakki Mert Torun; Kallol Roy; Madhavan Swaminathan; et al. (DAC, 2019)

A Spectral Convolutional Net for Co-Optimization of Integrated Voltage Regulators and Embedded Inductors. - Hakki Mert Torun; Huan Yu; Nihar Dasari; Venkata Chaitanya Krishna Chekuri; Arvind Singh; Jinwoo Kim; Sung Kyu Lim; Saibal Mukhopadhyay; Madhavan Swaminathan (ICCAD, 2019)

On the Effect of NBTI Induced Aging of Power Stage on the Transient Performance of On-Chip Voltage Regulators. - Venkata Chaitanya Krishna Chekuri; Arvind Singh; Nihar Dasari; Saibal Mukhopadhyay (IRPS, 2019)

Automatic GDSII Generator for On-Chip Voltage Regulator for Easy Integration in Digital SoCs. - Venkata Chaitanya Krishna Chekuri; Nihar Dasari; Arvind Singh; Saibal Mukhopadhyay (ISLPED, 2019)

Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse. - Jinwoo Kim; Gauthaman Murali; Heechun Park; Eric Qin 001; Hyoukjun Kwon; Venkata Chaitanya Krishna Chekuri; Nael Mizanur Rahman; Nihar Dasari; Arvind Singh; Minah Lee; Hakki Mert Torun; Kallol Roy; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2020)