Parallel A* Algorithms and Their Performance on Hypercube Multiprocessors. - Shantanu Dutt; Nihar R. Mahapatra (IPPS, 1993)

Scalable Duplicate Pruning Strategies for Parallel A* Graph Search. - Nihar R. Mahapatra; Shantanu Dutt (SPDP, 1993)

New Anticipatory Load Balancing Strategies for Parallel A* Algorithms. - Nihar R. Mahapatra; Shantanu Dutt (Parallel Processing of Discrete Optimization Problems, 1994)

Scalable Load Balancing Strategies for Parallel A* Algorithms. - Shantanu Dutt; Nihar R. Mahapatra (J. Parallel Distributed Comput., 1994)

Hardware-Efficient and Highly-Reconfigurable 4- and 2-Track: Fault-Tolerant Designs for Mesh-Connected Multicomputers. - Nihar R. Mahapatra; Shantanu Dutt (FTCS, 1996)

Node-Covering, Error-Correcting Codes and Multiprocessors with Very High Average Fault Tolerance. - Shantanu Dutt; Nihar R. Mahapatra (IEEE Trans. Computers, 1997)

Scalable Global and Local Hashing Strategies for Duplicate Pruning in Parallel A* Graph Search. - Nihar R. Mahapatra; Shantanu Dutt (IEEE Trans. Parallel Distributed Syst., 1997)

Efficient Network-Flow Based Techniques for Dynamic Fault Reconfiguration in FPGAs. - Nihar R. Mahapatra; Shantanu Dutt (FTCS, 1999)

A Quantitative Evaluation of Limited-Memory Branch-and-Bound Algorithms. - Nihar R. Mahapatra; Douglas E. Covelli; Yuval Beres (IC-AI, 1999)

The role of computer technology trends in computer architecture education. - Nihar R. Mahapatra; Alwin Tareen (WCAE@HPCA, 1999)

The processor-memory bottleneck: problems and solutions. - Nihar R. Mahapatra; Balakrishna V. Venkatrao (XRDS, 1999)

Efficient techniques based on gate triggering for designing static CMOS ICs with very low glitch power dissipation. - Nihar R. Mahapatra; Sriram V. Garimella; Alwin Takeen (ISCAS, 2000)

Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing. - Nihar R. Mahapatra; Shantanu Dutt (Int. J. Found. Comput. Sci., 2000)

Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays. - Nihar R. Mahapatra; Shantanu Dutt (J. Parallel Distributed Comput., 2001)

The performance advantage of applying compression to the memory system. - Nihar R. Mahapatra; Jiangjiang Liu 002; Krishnan Sundaresan (MSP/ISMM, 2002)

A Study of Hardware Techniques That Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units. - Kaushal R. Gandhi; Nihar R. Mahapatra (ICCD, 2003)

Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis. - Nihar R. Mahapatra; Jiangjiang Liu 002; Krishnan Sundaresan (ICCD, 2003)

The potential of compression to improve memory system performance, power consumption, and cost. - Nihar R. Mahapatra; Jiangjiang Liu 002; Krishnan Sundaresan; Srinivas Dangeti; Balakrishna V. Venkatrao (IPCCC, 2003)

Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses. - Jiangjiang Liu 002; Nihar R. Mahapatra; Krishnan Sundaresan (ISVLSI, 2003)

Code Compression Techniques for Embedded Systems and Their Effectiveness. - Krishnan Sundaresan; Nihar R. Mahapatra (ISVLSI, 2003)

A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits. - Srivathsan Krishnamohan; Nihar R. Mahapatra (ICCD, 2004)

Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study. - Jiangjiang Liu 002; Krishnan Sundaresan; Nihar R. Mahapatra (ICCD, 2004)

An efficient error-masking technique for improving the soft-error robustness of static CMOS circuits. - Srivathsan Krishnamohan; Nihar R. Mahapatra (SoCC, 2004)

Adaptive Quality Equalizing: High-performance load balancing for parallel branch-and-bound across applications and computing systems. - Nihar R. Mahapatra; Shantanu Dutt (Parallel Comput., 2004)

Combining Error Masking and Error Detection Plus Recovery to Combat Soft Errors in Static CMOS Circuits. - Srivathsan Krishnamohan; Nihar R. Mahapatra (DSN, 2005)

Analysis and design of soft-error hardened latches. - Srivathsan Krishnamohan; Nihar R. Mahapatra (ACM Great Lakes Symposium on VLSI, 2005)

An analysis of the robustness of CMOS delay elements. - Srivathsan Krishnamohan; Nihar R. Mahapatra (ACM Great Lakes Symposium on VLSI, 2005)

Increasing the energy efficiency of pipelined circuits via slack redistribution. - Srivathsan Krishnamohan; Nihar R. Mahapatra (ACM Great Lakes Symposium on VLSI, 2005)

Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses. - Krishnan Sundaresan; Nihar R. Mahapatra (HPCA, 2005)

Dynamically Exploiting Frequent Operand Values for Energy Efficiency in Integer Functional Units. - Kaushal R. Gandhi; Nihar R. Mahapatra (VLSI Design, 2005)

Energy-Efficient Compressed Address Transmission. - Jiangjiang Liu 002; Krishnan Sundaresan; Nihar R. Mahapatra (VLSI Design, 2005)

An Accurate Energy and Thermal Model for Global Signal Buses. - Krishnan Sundaresan; Nihar R. Mahapatra (VLSI Design, 2005)

A Limit Study on the Potential of Compression for Improving Memory System Performance, Power Consumption, and Cost. - Nihar R. Mahapatra; Jiangjiang Liu 002; Krishnan Sundaresan; Srinivas Dangeti; Balakrishna V. Venkatrao (J. Instr. Level Parallelism, 2005)

Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits. - Kaushal R. Gandhi; Nihar R. Mahapatra (DATE, 2006)

Value-based bit ordering for energy optimization of on-chip global signal buses. - Krishnan Sundaresan; Nihar R. Mahapatra (DATE, 2006)

Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction. - Jiangjiang Liu 002; Krishnan Sundaresan; Nihar R. Mahapatra (ACM Great Lakes Symposium on VLSI, 2006)

Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses. - Jiangjiang Liu 002; Krishnan Sundaresan; Nihar R. Mahapatra (ICCD, 2006)

An Analysis of Timing Violations Due to Spatially Distributed Thermal Effects in Global Wires. - Krishnan Sundaresan; Nihar R. Mahapatra (DAC, 2007)

Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses. - Sharath Jayaprakash; Nihar R. Mahapatra (VLSI Design, 2007)

An efficient delay-optimal distributed termination detection algorithm. - Nihar R. Mahapatra; Shantanu Dutt (J. Parallel Distributed Comput., 2007)

Enhancing Available-Memory Cost-Bounded Iterative-Deepening Search. - Sandeep K. Namilikonda; Nihar R. Mahapatra (IC-AI, 2008)

Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses. - Krishnan Sundaresan; Nihar R. Mahapatra (ISQED, 2008)

Partitioned reuse cache for energy-efficient soft-error protection of functional units. - Kaushal R. Gandhi; Nihar R. Mahapatra (SoCC, 2008)

Energy-optimal signaling and ordering of bits for area-constrained interconnects. - Sharath Jayaprakash; Nihar R. Mahapatra (SoCC, 2008)

Slack redistribution in pipelined circuits for enhanced soft-error rate reduction. - Srivathsan Krishnamohan; Nihar R. Mahapatra (SoCC, 2008)

The role of interconnects in the performance scalability of multicore architectures. - Jiangjiang Liu 002; Nihar R. Mahapatra (SoCC, 2008)

Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation Bypass. - Kaushal R. Gandhi; Nihar R. Mahapatra (VLSI Design, 2008)

An Instance-Based Learning Approach for Available-Memory Non-minimal Cost-Bounded Search. - Sandeep K. Namilikonda; Nihar R. Mahapatra (ICMLA, 2009)

Dynamic User-Driven Available-Memory Non-Minimal Cost-Bounded Search. - Sandeep K. Namilikonda; Nihar R. Mahapatra (IICAI, 2009)

Energy-Efficient Encoding for High-Performance Buses with Staggered Repeaters. - Sharath Jayaprakash; Nihar R. Mahapatra (ISVLSI, 2009)

Interconnect system compression analysis for multi-core architectures. - Jiangjiang Liu 002; Jianyong Zhang; Nihar R. Mahapatra (SoCC, 2010)

A Comparative Assessment of Conventional and Machine-Learning-Based Scoring Functions in Predicting Binding Affinities of Protein-Ligand Complexes. - Hossam M. Ashtawy; Nihar R. Mahapatra (BIBM, 2011)

A Comparative Assessment of Ranking Accuracies of Conventional and Machine-Learning-Based Scoring Functions for Protein-Ligand Binding Affinity Prediction. - Hossam M. Ashtawy; Nihar R. Mahapatra (IEEE ACM Trans. Comput. Biol. Bioinform., 2012)

Molecular Docking for Drug Discovery: Machine-Learning Approaches for Native Pose Prediction of Protein-Ligand Complexes. - Hossam M. Ashtawy; Nihar R. Mahapatra (CIBB, 2013)

Does Accurate Scoring of Ligands against Protein Targets Mean Accurate Ranking? - Hossam M. Ashtawy; Nihar R. Mahapatra (ISBRA, 2013)

BgN-Score and BsN-Score: Bagging and boosting based ensemble neural networks scoring functions for accurate binding affinity prediction of protein-ligand complexes. - Hossam M. Ashtawy; Nihar R. Mahapatra (BMC Bioinform., 2015)

Machine-learning scoring functions for identifying native poses of ligands docked to known and novel proteins. - Hossam M. Ashtawy; Nihar R. Mahapatra (BMC Bioinform., 2015)

A Comparative Assessment of Predictive Accuracies of Conventional and Machine Learning Scoring Functions for Protein-Ligand Binding Affinity Prediction. - Hossam M. Ashtawy; Nihar R. Mahapatra (IEEE ACM Trans. Comput. Biol. Bioinform., 2015)

Boosted neural networks scoring functions for accurate ligand docking and ranking. - Hossam M. Ashtawy; Nihar R. Mahapatra (J. Bioinform. Comput. Biol., 2018)

Task-Specific Scoring Functions for Predicting Ligand Binding Poses and Affinity and for Screening Enrichment. - Hossam M. Ashtawy; Nihar R. Mahapatra (J. Chem. Inf. Model., 2018)

Descriptor Data Bank (DDB): A Cloud Platform for Multiperspective Modeling of Protein-Ligand Interactions. - Hossam M. Ashtawy; Nihar R. Mahapatra (J. Chem. Inf. Model., 2018)

Modeling the Automation Level of Cyber-Physical Systems Designed for Food Preparation. - Dena F. Mujtaba; Nihar R. Mahapatra (ISED, 2019)

Analysis of Affordance Detection Methods for Real-World Robotic Manipulation. - Xavier Williams; Nihar R. Mahapatra (ISED, 2019)

Ethical Considerations in AI-Based Recruitment. - Dena F. Mujtaba; Nihar R. Mahapatra (ISTAS, 2019)

Multi-Task Deep Neural Networks for Multimodal Personality Trait Prediction. - Dena F. Mujtaba; Nihar R. Mahapatra (CSCI, 2021)

Lateral Flow Test Interpretation with Residual Networks. - Dena F. Mujtaba; Nihar R. Mahapatra (CSCI, 2021)

Convolutional Neural Networks for Morphologically Similar Fish Species Identification. - Dena F. Mujtaba; Nihar R. Mahapatra (CSCI, 2021)

Fish Species Classification with Data Augmentation. - Dena F. Mujtaba; Nihar R. Mahapatra (CSCI, 2021)

Multi-objective optimization of item selection in computerized adaptive testing. - Dena F. Mujtaba; Nihar R. Mahapatra (GECCO, 2021)

Deep Learning for Spatiotemporal Modeling of Illegal, Unreported, and Unregulated Fishing Events. - Dena F. Mujtaba; Nihar R. Mahapatra (CSCI, 2022)

A Study of Feature Importance in Fish Species Prediction Neural Networks. - Dena F. Mujtaba; Nihar R. Mahapatra (CSCI, 2022)

Hierarchical Deep Learning Models for Identification of Fish Species. - Dena F. Mujtaba; Nihar R. Mahapatra (CSCI, 2022)

Inclusive ASR for Disfluent Speech: Cascaded Large-Scale Self-Supervised Learning with Targeted Fine-Tuning and Data Augmentation. - Dena F. Mujtaba; Nihar R. Mahapatra; Megan Arney; J. Scott Yaruss; Caryn Herring; Jia Bin (INTERSPEECH, 2024)

Lost in Transcription: Identifying and Quantifying the Accuracy Biases of Automatic Speech Recognition Systems Against Disfluent Speech. - Dena F. Mujtaba; Nihar R. Mahapatra; Megan Arney; J. Scott Yaruss; Hope Gerlach-Houck; Caryn Herring; Jia Bin (NAACL-HLT, 2024)

Fairness in AI-Driven Recruitment: Challenges, Metrics, Methods, and Future Directions. - Dena F. Mujtaba; Nihar R. Mahapatra (CoRR, 2024)

Behind the Screens: Uncovering Bias in AI-Driven Video Interview Assessments Using Counterfactuals. - Dena F. Mujtaba; Nihar R. Mahapatra (CoRR, 2025)

Fine-Tuning ASR for Stuttered Speech: Personalized vs. Generalized Approaches. - Dena F. Mujtaba; Nihar R. Mahapatra (CoRR, 2025)