Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics. - Nihar R. Mohapatra; Arijit Dutta; Madhav P. Desai; V. Ramgopal Rao (VLSI Design, 2001)

Sub-100 nm CMOS circuit performance with high-K gate dielectrics. - Nihar R. Mohapatra; Arijit Dutta; G. Sridhar; Madhav P. Desai; V. Ramgopal Rao (Microelectron. Reliab., 2001)

Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits. - D. Vinay Kumar; Nihar R. Mohapatra; Mahesh B. Patil; V. Ramgopal Rao (VLSI Design, 2003)

Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics. - Nihar R. Mohapatra; Madhav P. Desai; V. Ramgopal Rao (VLSI Design, 2003)

Novel design of a silicon photodetector and its integration in a 4×4 CMOS pixel array. - Hari Shanker Gupta; Satyajit Mohapatra; Nihar R. Mohapatra; Dinesh Kumar Sharma (ISQED, 2016)

Analysis and Modeling of Stress over Layer Induced Threshold Voltage Shift in HKMG nMOS Transistors. - Apoorva Ojha; Narendra Parihar; Nihar R. Mohapatra (VLSID, 2016)

Trap-assisted carrier transport through the multi-stack gate dielectrics of HKMG nMOS transistors: A compact model. - Apoorva Ojha; Nihar R. Mohapatra (ESSDERC, 2017)

Performance Optimized 64b/66b Line Encoding Technique for High Speed SERDES Devices. - Jatindeep Singh; Satyajit Mohapatra; Nihar Ranjan Mohapatra (VDAT, 2017)

Low-Power Sequential Circuit Design Using Work-Function Engineered FinFETs. - Ashish Soni; Abhijit Umap; Nihar R. Mohapatra (VDAT, 2017)

A 64b/66b Line Encoding for High Speed Serializers. - Satyajit Mohapatra; Hari Shanker Gupta; Jatindeep Singh; Nihar Ranjan Mohapatra (VLSID, 2017)

An Ultra Energy Efficient Neuron enabled by Tunneling in Sub-threshold Regime on a Highly Manufacturable 32 nm SOI CMOS Technology. - Tanmay Chavan; S. Dutta; Nihar R. Mohapatra; Udayan Ganguly (DRC, 2018)

Mismatch Resilient 3.5-Bit MDAC with MCS-CFCS. - Satyajit Mohapatra; Hari Shanker Gupta; Nihar Ranjan Mohapatra (ISVLSI, 2018)

The HotSpot Compensation in High Speed Data Converters. - Satyajit Mohapatra; Nihar Ranjan Mohapatra (MWSCAS, 2018)

Capacitance and Surface Potential Model for III-V Double-Gate FET. - Sarath Chandran G. M; Mohit D. Ganeriwala; Nihar Ranjan Mohapatra (ISDCS, 2019)

Design and Calibration of 14-bit 10 KS/s Low Power SAR ADC for Bio-medical Applications. - Yadukrishnan Mekkattillam; Satyajit Mohapatra; Nihar R. Mohapatra (VDAT, 2019)

An Unified Charge Centroid Model for Silicon and Low Effective Mass III-V Channel Double Gate MOS Transistors. - Amratansh Gupta; Mohit Ganeriwala; Nihar Ranjan Mohapatra (VLSID, 2019)

A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADC. - Satyajit Mohapatra; Hari Shanker Gupta; Nihar Ranjan Mohapatra; Sanjeev Mehta; Arup Roy Chowdhury; Nisha Pandya (VLSID, 2019)

Band-to-Band Tunneling based Ultra-Energy Efficient Silicon Neuron. - Tanmay Chavan; Sangya Dutta; Nihar R. Mohapatra; Udayan Ganguly (CoRR, 2019)

The Design of Ultra Low Power SAR ADC for Implantable Cardioverter Defibrillator (ICD). - Satyajit Mohapatra; Nihar Ranjan Mohapatra (VLSID, 2020)

Gradient Error Compensation in SC-MDACs. - Satyajit Mohapatra; Nihar Ranjan Mohapatra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Behavior of LDMOS transistors at cryogenic temperature - An experiment based analysis. - Kaushal Kumari Neeraj; Nihar Ranjan Mohapatra (VDAT, 2021)

High Resolution Temperature Sensor Signal Processing ASIC for Cryo-Cooler Electronics. - Anuj Srivastava; Nishant Kumar; Nihar Ranjan Mohapatra; Hari Shankar Gupta (VDAT, 2022)

Dispersion in Placement: Quantification and Insights. - Satyajit Mohapatra; Nihar Ranjan Mohapatra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Sub-nanosecond Delay High Voltage Level Shifter in 0.18μm HV-CMOS Technology for Cryo-Cooler Electronics. - Nishant Kumar; Hari Shanker Gupta; Nilesh M. Desai; Nihar Ranjan Mohapatra (APCCAS, 2023)

Process Voltage Temperature Variability Estimation of Tunneling Current for Band-to-Band-Tunneling based Neuron. - Shubham Patil; Anand Sharma; Gaurav R; Abhishek Kadam; Ajay Kumar Singh; Sandip Lashkare; Nihar Ranjan Mohapatra; Udayan Ganguly (CoRR, 2023)

A Programmable and Adaptive Dead-Time Controller for Low-Offset Output Generation for Cryo-Cooler Drive Applications. - Nishant Kumar; Hari Shanker Gupta; Anuj Srivastava; Nihar Ranjan Mohapatra (ISCAS, 2024)

K-means Clustering with ANN based Classification to Predict Current-Voltage Characteristics of Advanced FETs. - Om Maheshwari; Dev Vyas; Nihar Ranjan Mohapatra (VLSID, 2024)

On the improved RF performance of step field plate LDMOS transistor. - Rutu Patel; Nihar R. Mohapatra (Microelectron. J., 2024)

Reliable High-Performance Programmable Voltage Regulator with 0.55A Sink Current for Cryo-Cooler Electronics in 0.18μm HV-CMOS Technology. - Nishant Kumar; Hari Shanker Gupta; Nihar Ranjan Mohapatra (VLSID, 2025)

Exploring the impact of sheet thickness scaling on Nanosheet FET gate electrostatics using k.p based simulations. - Ramandeep Kaur; Nihar R. Mohapatra (Microelectron. J., 2025)