A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree. - Niichi Itoh; Yuka Naemura; Hiroshi Makino; Yasunobu Nakase; Tsutomu Yoshihara; Yasutaka Horiba (IEEE J. Solid State Circuits, 2001)

A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. - Niichi Itoh; Yasumasa Tsukamoto; Takeshi Shibagaki; Koji Nii; Hidehiro Takata; Hiroshi Makino (ISCAS (1), 2005)