A performance analytical model for Network-on-Chip with constant service time routers. - Nikita Nikitin; Jordi Cortadella (ICCAD, 2009)

Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing. - Nikita Nikitin; Satrajit Chatterjee; Jordi Cortadella; Michael Kishinevsky; Ümit Y. Ogras (NOCS, 2010)

Static Task Mapping for Tiled Chip Multiprocessors with Multiple Voltage Islands. - Nikita Nikitin; Jordi Cortadella (ARCS, 2012)

Analytical Performance Modeling of Hierarchical Interconnect Fabrics. - Nikita Nikitin; Javier de San Pedro; Josep Carmona 001; Jordi Cortadella (NOCS, 2012)

Physical-aware system-level design for tiled hierarchical chip multiprocessors. - Jordi Cortadella; Javier de San Pedro; Nikita Nikitin; Jordi Petit (ISPD, 2013)

Physical planning for the architectural exploration of large-scale chip multiprocessors. - Javier de San Pedro; Nikita Nikitin; Jordi Cortadella; Jordi Petit (NOCS, 2013)

Architectural Exploration of Large-Scale Hierarchical Chip Multiprocessors. - Nikita Nikitin; Javier de San Pedro; Jordi Cortadella (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Automatic synthesis and optimization of chip multiprocessors. - Nikita Nikitin (2013)

Load scheduling in smart buildings with bidirectional energy trading. - Abdullah Al Hasib; Nikita Nikitin; Lasse Natvig (IPCCC, 2014)

Patterned Heterogeneous CMPs: The Case for Regularity-Driven System-Level Synthesis. - Nikita Nikitin; Magnus Jahre (ISVLSI, 2014)

Cost-comfort balancing in a smart residential building with bidirectional energy trading. - Abdullah Al Hasib; Nikita Nikitin; Lasse Natvig (SustainIT, 2015)

Developing Lightweight DNN Models With Limited Data For Real-Time Sign Language Recognition. - Nikita Nikitin; Eugene Fomin (CoRR, 2025)