Dynamic Flip-Flop with Improved Power. - Nikola Nedovic; Vojin G. Oklobdzija (ICCD, 2000)

Hybrid latch Flip-Flop with Improved Power Efficiency. - Nikola Nedovic; Vojin G. Oklobdzija (SBCCI, 2000)

Timing Characterization of Dual-edge Triggered Flip-flops. - Nikola Nedovic; Marko Aleksic; Vojin G. Oklobdzija (ICCD, 2001)

Conditional techniques for low power consumption flip-flops. - Nikola Nedovic; Marko Aleksic; Vojin G. Oklobdzija (ICECS, 2001)

Comparative analysis of double-edge versus single-edge triggered clocked storage elements. - Nikola Nedovic; Marko Aleksic; Vojin G. Oklobdzija (ISCAS (5), 2002)

Conditional pre-charge techniques for power-efficient dual-edge clocking. - Nikola Nedovic; Marko Aleksic; Vojin G. Oklobdzija (ISLPED, 2002)

A test circuit for measurement of clocked storage element characteristics. - Nikola Nedovic; William W. Walker; Vojin G. Oklobdzija (IEEE J. Solid State Circuits, 2004)

A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers. - Marko Aleksic; Nikola Nedovic; K. Wayne Current; Vojin G. Oklobdzija (PATMOS, 2005)

Dual-edge triggered storage elements and clocking strategy for low-power systems. - Nikola Nedovic; Vojin G. Oklobdzija (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations. - Christophe Giacomotto; Nikola Nedovic; Vojin G. Oklobdzija (PATMOS, 2006)

A 40-to-44Gb/s 3? Oversampling CMOS CDR/1: 16 DEMUX. - Nikola Nedovic; Nestoras Tzartzanis; Hirotaka Tamura; Francis M. Rotella; Magnus Wiklund; Yuma Mizutani; Yusuke Okaniwa; Tadahiro Kuroda; Junji Ogawa; William W. Walker (ISSCC, 2007)

The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements. - Christophe Giacomotto; Nikola Nedovic; Vojin G. Oklobdzija (IEEE J. Solid State Circuits, 2007)

A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX. - Nikola Nedovic; Nestoras Tzartzanis; Hirotaka Tamura; Francis M. Rotella; Magnus Wiklund; Yuma Mizutani; Yusuke Okaniwa; Tadahiro Kuroda; Junji Ogawa; William W. Walker (IEEE J. Solid State Circuits, 2007)

Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits. - Marko Aleksic; Nikola Nedovic; K. Wayne Current; Vojin G. Oklobdzija (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. - Nikola Nedovic; Anders Kristensson; Samir Parikh; Subodh M. Reddy; Scott McLeod; Nestoras Tzartzanis; Kouichi Kanda; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Satoshi Ide; et al. (IEEE J. Solid State Circuits, 2010)

A DC-46Gb/s 2: 1 multiplexer and source-series terminated driver in 20nm CMOS technology. - Jian Hong Jiang; Samir Parikh; Mark Lionbarger; Nikola Nedovic; Takuji Yamamoto (A-SSCC, 2014)

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. - Walker J. Turner; John W. Poulton; John M. Wilson 002; Xi Chen 033; Stephen G. Tell; Matthew Fojtik; Thomas H. Greer; Brian Zimmer; Sanquan Song; Nikola Nedovic; Sudhir S. Kudva; Sunil R. Sudhakaran; et al. (CICC, 2018)

A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. - John M. Wilson 002; Walker J. Turner; John W. Poulton; Brian Zimmer; Xi Chen 033; Sudhir S. Kudva; Sanquan Song; Stephen G. Tell; Nikola Nedovic; Wenxu Zhao; Sunil R. Sudhakaran; C. Thomas Gray; et al. (ISSCC, 2018)

Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET. - Xi Chen 033; Sanquan Song; John Poulton; Nikola Nedovic; Brian Zimmer; Stephen G. Tell; C. Thomas Gray (CICC, 2019)

A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. - Sanquan Song; John Poulton; Xi Chen 033; Brian Zimmer; Stephen G. Tell; Walker J. Turner; Sudhir S. Kudva; Nikola Nedovic; John M. Wilson 002; C. Thomas Gray; William J. Dally (CICC, 2019)

Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference. - Angad S. Rekhi; Brian Zimmer; Nikola Nedovic; Ningxi Liu; Rangharajan Venkatesan; Miaorong Wang; Brucek Khailany; William J. Dally; C. Thomas Gray (DAC, 2019)

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. - John W. Poulton; John M. Wilson 002; Walker J. Turner; Brian Zimmer; Xi Chen 033; Sudhir S. Kudva; Sanquan Song; Stephen G. Tell; Nikola Nedovic; Wenxu Zhao; Sunil R. Sudhakaran; C. Thomas Gray; et al. (IEEE J. Solid State Circuits, 2019)

6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links. - Xi Chen 033; Nikola Nedovic; Stephen G. Tell; Sudhir S. Kudva; Brian Zimmer; Thomas H. Greer; John W. Poulton; Sanquan Song; Walker J. Turner; John M. Wilson 002; C. Thomas Gray (ISSCC, 2020)

A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS. - Yoshinori Nishi; John W. Poulton; Xi Chen 033; Sanquan Song; Brian Zimmer; Walker J. Turner; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (VLSI Technology and Circuits, 2022)

An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process. - Sanquan Song; Stephen G. Tell; Brian Zimmer; Sudhir S. Kudva; Nikola Nedovic; C. Thomas Gray (VLSI Technology and Circuits, 2022)

A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS. - Yoshinori Nishi; John W. Poulton; Walker J. Turner; Xi Chen 033; Sanquan Song; Brian Zimmer; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (IEEE J. Solid State Circuits, 2023)

16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking. - Sudhir S. Kudva; Mahmut Ersin Sinangil; Stephen G. Tell; Nikola Nedovic; Sanquan Song; Brian Zimmer; C. Thomas Gray (ISSCC, 2024)

A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. - Yoshinori Nishi; John W. Poulton; Walker J. Turner; Xi Chen 033; Sanquan Song; Brian Zimmer; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (IEEE J. Solid State Circuits, 2024)