Timing Extensions of STG Model and a Method to Simulate Timed STG Behavior in VHDL Environment. - Michael V. Goncharov; Alexander B. Smirnov; Nikolai Starodoubtsev; Ilya V. Klotchkov (ACSD, 1998)

Semi-modular Latch Chains for Asynchronous Circuit Design. - Nikolai Starodoubtsev; Alexandre V. Bystrov; Alexandre Yakovlev (PATMOS, 2000)

Towards Synthesis of Monotonic Asynchronous Circuits from Signal Transition Graphs. - Nikolai Starodoubtsev; Sergei Bystrov; Michael V. Goncharov; Ilya V. Klotchkov; Alexander B. Smirnov (ACSD, 2001)

Monotonic Circuits with Complete Acknowledgement. - Nikolai Starodoubtsev; Sergei Bystrov; Alexandre Yakovlev (ASYNC, 2003)

Behavior and Synthesis of Two-Input Gate Asynchronous Circuits. - Nikolai Starodoubtsev; Sergei Bystrov (ASYNC, 2005)