Timing Errors in STA-based Gate-Level Simulation. - Stavros Simoglou; Christos P. Sotiriou; Nikolaos Blias (ASYNC, 2020)

Static Timing Analysis Induced Simulation Errors for Asynchronous Circuits. - Stavros Simoglou; Christos P. Sotiriou; Nikolaos Blias (DFT, 2021)

Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis Flows. - Nikolaos Blias; Iordanis Lilitsis; Stavros Simoglou; Evangelos Bakas; Christos P. Sotiriou (VLSI-SoC, 2022)

Full Stage Delay Calculation Using Full Waveform Propagation and Standard Library CCS Model. - Stavros Simoglou; Iordanis Lilitsis; Nikolaos Blias; Christos P. Sotiriou (ISQED, 2024)