Simulation-Based Maximum Coverage Hazard Detection and Elimination Analysis, Supporting Combinational Logic Loops. - Nikolaos Chatzivangelis; Dimitris Valiantzas; Christos P. Sotiriou; Iordanis Lilitsis (VLSI-SoC, 2022)

Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis. - Christos Georgakidis; Dimitris Valiantzas; Stavros Simoglou; Iordanis Lilitsis; Nikolaos Chatzivangelis; Ilias Golfos; Marko S. Andjelkovic; Christos P. Sotiriou; Milos Krstic (DFT, 2023)

Post-Placement Timing Optimisations on Asynchronous Designs. - Dimitrios Tsalapatas; Nikolaos Chatzivangelis; Christos P. Sotiriou; Nikolaos Sketopoulos (ASYNC, 2025)

Multi-Partner Project: Twinning for Excellence in Reliable Electronics (TWIN-RELECT). - Marko S. Andjelkovic; Fabian Vargas 001; Milos Krstic; Luigi Dilillo; Alain Michez; Frederic Wrobel; Davide Bertozzi; Mikel Luján; Christos Georgakidis; Nikolaos Chatzivangelis; Katerina Tsilingiri; Nikolaos Zazatis; et al. (DATE, 2025)