Effectiveness evaluation of the TSV fault detection method using ring oscillators. - Nikolaos Georgoulopoulos; Alkiviadis A. Hatzopoulos (MOCAST, 2017)

Efficiency evaluation of a SystemVerilog-based real number model. - Nikolaos Georgoulopoulos; Alkiviadis A. Hatzopoulos (MOCAST, 2018)

UVM-Based Verification of a Mixed-Signal Design Using SystemVerilog. - Nikolaos Georgoulopoulos; Ioannis Giannou; Alkiviadis A. Hatzopoulos (PATMOS, 2018)

Design of a SystemVerilog-Based Sigma-Delta ADC Real Number Model. - Constantina Tsechelidou; Nikolaos Georgoulopoulos; Alkiviadis A. Hatzopoulos (DSD, 2019)

Design of a Digital PLL Real Number Model Using SystemVerilog. - Nikolaos Georgoulopoulos; Alkiviadis A. Hatzopoulos (MOCAST, 2019)

Design of a SystemVerilog-Based VCO Real Number Model. - Nikolaos Georgoulopoulos; Athanasios Mekras; Alkiviadis A. Hatzopoulos (MOCAST, 2019)

UVM-based Verification of a Digital PLL Using SystemVerilog. - Nikolaos Georgoulopoulos; Alkiviadis A. Hatzopoulos (PATMOS, 2019)

A Survey on Hardware Failure Prediction of Servers Using Machine Learning and Deep Learning. - Nikolaos Georgoulopoulos; Alkiviadis A. Hatzopoulos; Konstantinos Karamitsios; Irene-Maria Tabakis; Konstantinos Kotrotsios; Alexandros I. Metsai (MOCAST, 2021)

Investigation and Simulation of Hardware Errors in Kernel Logs of Linux-based Server Systems. - Nikolaos Georgoulopoulos; Alkis A. Hatzopoulos; Konstantinos Karamitsios; Irene-Maria Tabakis; Konstantinos Kotrotsios; Alexandros I. Metsai (SEEDA-CECNSM, 2021)

Parameterizable Real Number Models for Mixed-Signal Designs Using SystemVerilog. - Nikolaos Georgoulopoulos; Alkiviades A. Hatzopoulos (J. Electron. Test., 2021)

Design and Verification of a SAR ADC SystemVerilog Real Number Model. - Nikolaos Georgoulopoulos; Theodora Mamali; Alkis A. Hatzopoulos (J. Electron. Test., 2024)