Nikos Hardavellas

Orcid: 0000-0002-1137-8100

Affiliations:
  • Northwestern University, Department of Computer Science, Evanston, IL, USA
  • Carnegie Mellon University, Pittsburgh, USA


According to our database1, Nikos Hardavellas authored at least 70 papers between 1993 and 2023.

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Bibliography

2023
Evaluating Functional Memory-Managed Parallel Languages for HPC using the NAS Parallel Benchmarks.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

Generalized Collective Algorithms for the Exascale Era.
Proceedings of the IEEE International Conference on Cluster Computing, 2023

WARDen: Specializing Cache Coherence for High-Level Parallel Languages.
Proceedings of the 21st ACM/IEEE International Symposium on Code Generation and Optimization, 2023

Parsimony: Enabling SIMD/Vector Programming in Standard Compiler Flows.
Proceedings of the 21st ACM/IEEE International Symposium on Code Generation and Optimization, 2023

Program State Element Characterization.
Proceedings of the 21st ACM/IEEE International Symposium on Code Generation and Optimization, 2023

2022
A Practical Shared Optical Cache With Hybrid MWSR/R-SWMR NoC for Multicore Processors.
ACM J. Emerg. Technol. Comput. Syst., 2022

SupermarQ: A Scalable Quantum Benchmark Suite.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

ACCLAiM: Advancing the Practicality of MPI Collective Communication Autotuning Using Machine Learning.
Proceedings of the IEEE International Conference on Cluster Computing, 2022

CARAT CAKE: replacing paging via compiler/kernel cooperation.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2021
Public Release and Validation of SPEC CPU2017 PinPoints.
CoRR, 2021

Energy-Proportional Data Center Network Architecture Through OS, Switch and Laser Co-design.
CoRR, 2021

The Case for an Interwoven Parallel Hardware/Software Stack.
Proceedings of the 2021 SC Workshops Supplementary Proceedings, 2021

Task parallel assembly language for uncompromising parallelism.
Proceedings of the PLDI '21: 42nd ACM SIGPLAN International Conference on Programming Language Design and Implementation, 2021

AccelWattch: A Power Modeling Framework for Modern GPUs.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Pho$: A Case for Shared Optical Cache Hierarchies.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

A FACT-based Approach: Making Machine Learning Collective Autotuning Feasible on Exascale Systems.
Proceedings of the Workshop on Exascale MPI, 2021

ST<sup>2</sup> GPU: An Energy-Efficient GPU Design with Spatio-Temporal Shared-Thread Speculative Adders.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
CARAT: a case for virtual memory through compiler- and runtime-based address translation.
Proceedings of the 41st ACM SIGPLAN International Conference on Programming Language Design and Implementation, 2020

2019
Prospects for Functional Address Translation.
Proceedings of the 27th IEEE International Symposium on Modeling, 2019

Paths to Fast Barrier Synchronization on the Node.
Proceedings of the 28th International Symposium on High-Performance Parallel and Distributed Computing, 2019

2018
Stop-&-Go Operator.
Proceedings of the Encyclopedia of Database Systems, Second Edition, 2018

Operator-Level Parallelism.
Proceedings of the Encyclopedia of Database Systems, Second Edition, 2018

Intra-query Parallelism.
Proceedings of the Encyclopedia of Database Systems, Second Edition, 2018

Inter-query Parallelism.
Proceedings of the Encyclopedia of Database Systems, Second Edition, 2018

Execution Skew.
Proceedings of the Encyclopedia of Database Systems, Second Edition, 2018

Temporal Approximate Function Memoization.
IEEE Micro, 2018

Unconventional Parallelization of Nondeterministic Applications.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
VaLHALLA: Variable Latency History Aware Local-carry Lazy Adder.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

POSTER: The Liberation Day of Nondeterministic Programs.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
Energy-Proportional Photonic Interconnects.
ACM Trans. Archit. Code Optim., 2016

SLaC: Stage laser control for a flattened butterfly network.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

Lazy Pipelines: Enhancing quality in approximate computing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Evaluation of K-means data clustering algorithm on Intel Xeon Phi.
Proceedings of the 2016 IEEE International Conference on Big Data (IEEE BigData 2016), 2016

2015
Parka: Thermally Insulated Nanophotonic Interconnects.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

SCP: Synergistic cache compression and prefetching.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

b-HiVE: a bit-level history-based error model with value correlation for voltage-scaled integer and floating point units.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Edge importance identification for energy efficient graph processing.
Proceedings of the 2015 IEEE International Conference on Big Data (IEEE BigData 2015), Santa Clara, CA, USA, October 29, 2015

2014
EcoLaser: an adaptive laser control for energy-efficient on-chip photonic interconnects.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Galaxy: a high-performance energy-efficient multi-chip architecture using photonic interconnects.
Proceedings of the 2014 International Conference on Supercomputing, 2014

2013
The Impact of Dynamic Directories on Multicore Interconnects.
Computer, 2013

2012
The Rise and Fall of Dark Silicon.
login Usenix Mag., 2012

Load balancing for processing spatio-temporal queries in multi-core settings.
Proceedings of the Eleventh ACM International Workshop on Data Engineering for Wireless and Mobile Access, 2012

Dynamic Directories: A mechanism for reducing on-chip interconnect power in multicores.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Toward Dark Silicon in Servers.
IEEE Micro, 2011

Elastic Fidelity: Trading-off Computational Accuracy for Energy Reduction
CoRR, 2011

Hardware/software techniques for DRAM thermal management.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

2010
Data-Oriented Transaction Execution.
Proc. VLDB Endow., 2010

Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures.
IEEE Micro, 2010

2009
Stop-&-go Operator.
Proceedings of the Encyclopedia of Database Systems, 2009

Operator-Level Parallelism.
Proceedings of the Encyclopedia of Database Systems, 2009

Intra-Query Parallelism.
Proceedings of the Encyclopedia of Database Systems, 2009

Inter-Query Parallelism.
Proceedings of the Encyclopedia of Database Systems, 2009

Execution Skew.
Proceedings of the Encyclopedia of Database Systems, 2009

Reactive NUCA: near-optimal block placement and replication in distributed caches.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Shore-MT: a scalable storage manager for the multicore era.
Proceedings of the EDBT 2009, 2009

2007
To Share or Not To Share?
Proceedings of the 33rd International Conference on Very Large Data Bases, 2007

Scheduling threads for constructive cache sharing on CMPs.
Proceedings of the SPAA 2007: Proceedings of the 19th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2007

Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding.
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

Database Servers on Chip Multiprocessors: Limitations and Opportunities.
Proceedings of the Third Biennial Conference on Innovative Data Systems Research, 2007

2006
Parallel depth first vs. work stealing schedulers on CMP architectures.
Proceedings of the SPAA 2006: Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Cambridge, Massachusetts, USA, July 30, 2006

2005
Temporal Streaming of Shared Memory.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Store-Ordered Streaming of Shared Memory.
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005

2004
SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture.
SIGMETRICS Perform. Evaluation Rev., 2004

Memory coherence activity prediction in commercial workloads.
Proceedings of the 3rd Workshop on Memory Performance Issues, 2004

1999
Cashmere-VLM: Remote Memory Paging for Software Distributed Shared Memory.
Proceedings of the 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 1999

1997
Cashmere-2L: Software Coherent Shared Memory on a Clustered Remote-Write Network.
Proceedings of the Sixteenth ACM Symposium on Operating System Principles, 1997

VM-Based Shared Memory on Low-Latency, Remote-Memory-Access Networks.
Proceedings of the 24th International Symposium on Computer Architecture, 1997

Understanding the Performance of DSM Applications.
Proceedings of the Communication and Architectural Support for Network-Based Parallel Computing, 1997

1994
Contention in Counting Networks.
Proceedings of the Thirteenth Annual ACM Symposium on Principles of Distributed Computing, 1994

1993
Notes on Sorting and Counting Networks (Extended Abstract).
Proceedings of the Distributed Algorithms, 7th International Workshop, 1993


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