FPGA Architecture Design and Toolset for Logic Implementation. - Konstantinos Tatas; Kostas Siozios; Nikolaos Vassiliadis; D. J. Soudris; Spiridon Nikolaidis 001; Stilianos Siskos; Adonios Thanailakis (PATMOS, 2003)

The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms. - Nikolaos Vassiliadis; A. Chormoviti; Nikolaos Kavvadias; Spiridon Nikolaidis 001 (PATMOS, 2004)

AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. - Dimitrios Soudris; Spiridon Nikolaidis 001; Stilianos Siskos; Konstantinos Tatas; Kostas Siozios; George Koutroumpezis; Nikolaos Vassiliadis; Vasilios Kalenteridis; Haroula Pournara; Ilias Pappas 001; Adonios Thanailakis (ASP-DAC, 2005)

A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications. - Kostas Siozios; George Koutroumpezis; Konstantinos Tatas; Nikolaos Vassiliadis; Vasilios Kalenteridis; Haroula Pournara; Ilias Pappas 001; Dimitrios Soudris; Antonios Thanailakis; Spiridon Nikolaidis 001; Stilianos Siskos (IEICE Trans. Inf. Syst., 2005)

The effect of Data-Reuse Transformations on Multimedia Applications for Application Specific Processors. - Nikolaos Vassiliadis; A. Chormoviti; Nikolaos Kavvadias; Spiridon Nikolaidis 001 (Int. J. Comput., 2005)

A complete platform and toolset for system implementation on fine-grain reconfigurable hardware. - Vasilios Kalenteridis; Haroula Pournara; Kostas Siozios; Konstantinos Tatas; Nikolaos Vassiliadis; Ilias Pappas 001; George Koutroumpezis; Spiridon Nikolaidis 001; Stilianos Siskos; D. J. Soudris (Microprocess. Microsystems, 2005)

Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support. - Nikolaos Vassiliadis; George Theodoridis; Spiridon Nikolaidis 001 (ARC, 2006)

An automated development framework for a RISC processor with reconfigurable instruction set extensions. - Nikolaos Vassiliadis; George Theodoridis; Spiridon Nikolaidis 001 (IPDPS, 2006)

The ARISE Reconfigurable Instruction Set Extensions Framework. - Nikolaos Vassiliadis; George Theodoridis; Spiridon Nikolaidis 001 (ICSAMOS, 2007)

ARISE Machines: Extending Processors with Hybrid Accelerators. - Nikolaos Vassiliadis; George Theodoridis; Spiridon Nikolaidis 001 (ARC, 2008)

An integer linear programming model for mapping applications on hybrid systems. - George Theodoridis; Nikolaos Vassiliadis; Spiridon Nikolaidis 001 (IET Comput. Digit. Tech., 2009)

An Application Development Framework for ARISE Reconfigurable Processors. - Nikolaos Vassiliadis; George Theodoridis; Spiridon Nikolaidis 001 (ACM Trans. Reconfigurable Technol. Syst., 2009)

The ARISE Approach for Extending Embedded Processors With Arbitrary Hardware Accelerators. - Nikolaos Vassiliadis; George Theodoridis; Spiridon Nikolaidis 001 (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Real-time canny edge detection parallel implementation for FPGAs. - Christos Gentsos; Calliope-Louisa Sotiropoulou; Spiridon Nikolaidis 001; Nikolaos Vassiliadis (ICECS, 2010)

FPGA-based machine vision implementation for Lab-on-Chip flow detection. - Calliope-Louisa Sotiropoulou; Liberis Voudouris; Christos Gentsos; Spiridon Nikolaidis 001; Nikolaos Vassiliadis; Athanasios M. Demiris; Spyros Blionas (ISCAS, 2012)

Real-Time Machine Vision FPGA Implementation for Microfluidic Monitoring on Lab-on-Chips. - Calliope-Louisa Sotiropoulou; Liberis Voudouris; Christos Gentsos; Athanasios M. Demiris; Nikolaos Vassiliadis; Spiridon Nikolaidis 001 (IEEE Trans. Biomed. Circuits Syst., 2014)