Software Accelerated Functional Fault Simulation for Data-Path Architectures. - Mark Kassab; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (DAC, 1995)

On testable multipliers for fixed-width data path architectures. - Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (ICCAD, 1995)

Arithmetic built-in self test for high-level synthesis. - Nilanjan Mukherjee 001; H. Kassab; Janusz Rajski; Jerzy Tyszer (VTS, 1995)

Parameterizable Testing Scheme for FIR Filters. - Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (ITC, 1997)

Design of Testable Multipliers for Fixed-Width Data Paths. - Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 1997)

A BIST scheme for the detection of path-delay faults. - Nilanjan Mukherjee 001; Tapan J. Chakraborty; Sudipta Bhawmik (ITC, 1998)

Built in self test: a complete test solution for telecommunication systems. - Nilanjan Mukherjee 001; Tapan J. Chakraborty; Ramesh Karri (IEEE Commun. Mag., 1999)

Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. - Yu Huang 005; Wu-Tung Cheng; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Yahya Zaidan; Sudhakar M. Reddy (Asian Test Symposium, 2001)

On RTL scan design. - Yu Huang 005; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Dan Devries; Wu-Tung Cheng; Sudhakar M. Reddy (ITC, 2001)

Testing Schemes for FIR Filter Structures. - Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 2001)

Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. - Yu Huang 005; Sudhakar M. Reddy; Wu-Tung Cheng; Paul Reuter; Nilanjan Mukherjee 001; Chien-Chung Tsai; Omer Samman; Yahya Zaidan (ITC, 2002)

Embedded Deterministic Test for Low-Cost Manufacturing Test. - Janusz Rajski; Jerzy Tyszer; Mark Kassab; Nilanjan Mukherjee 001; Rob Thompson; Kun-Han Tsai; Andre Hertwig; Nagesh Tamarapalli; Grzegorz Mrugalski; Geir Eide; Jun Qian (ITC, 2002)

Constraint Driven Pin Mapping for Concurrent SOC Testing. - Yu Huang 005; Nilanjan Mukherjee 001; Chien-Chung Tsai; Omer Samman; Yahya Zaidan; Yanping Zhang; Wu-Tung Cheng; Sudhakar M. Reddy (ASP-DAC/VLSI Design, 2002)

On Concurrent Test of Core-Based SOC Design. - Yu Huang 005; Wu-Tung Cheng; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Yahya Zaidan; Sudhakar M. Reddy (J. Electron. Test., 2002)

Synthesis of Scan Chains for Netlist Descriptions at RT-Level. - Yu Huang 005; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Wu-Tung Cheng; Sudhakar M. Reddy (J. Electron. Test., 2002)

Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. - Yu Huang 005; Wu-Tung Cheng; Chien-Chung Tsai; Nilanjan Mukherjee 001; Sudhakar M. Reddy (ISQED, 2003)

Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. - Frank Poehl; Matthias Beck; Ralf Arnold; Peter Muhmenthaler; Nagesh Tamarapalli; Mark Kassab; Nilanjan Mukherjee 001; Janusz Rajski (ITC, 2003)

Embedded Deterministic Test for Low-Cost Manufacturing. - Janusz Rajski; Mark Kassab; Nilanjan Mukherjee 001; Nagesh Tamarapalli; Jerzy Tyszer; Jun Qian (IEEE Des. Test Comput., 2003)

Cost of Test - Taking Control. - Nilanjan Mukherjee 001 (ITC, 2004)

At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories. - Xiaogang Du; Sudhakar M. Reddy; Wu-Tung Cheng; Joseph Rayhawk; Nilanjan Mukherjee 001 (VLSI Design, 2004)

Embedded Test for Low Cost Manufacturing. - Janusz Rajski; Nilanjan Mukherjee 001; Jerzy Tyszer; Thomas Rinderknecht (VLSI Design, 2004)

Planar High Performance Ring Generators. - Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (VTS, 2004)

Embedded deterministic test. - Janusz Rajski; Jerzy Tyszer; Mark Kassab; Nilanjan Mukherjee 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Achieving High Test Quality with Reduced Pin Count Testing. - Jay Jahangiri; Nilanjan Mukherjee 001; Wu-Tung Cheng; Subramanian Mahadevan; Ron Press (Asian Test Symposium, 2005)

Improving Test Quality Using Test Data Compression. - Nilanjan Mukherjee 001 (Asian Test Symposium, 2005)

Full-speed field-programmable memory BIST architecture. - Xiaogang Du; Nilanjan Mukherjee 001; Wu-Tung Cheng; Sudhakar M. Reddy (ITC, 2005)

Chasing subtle embedded RAM defects for nanometer technologies. - Theo J. Powell; Amrendra Kumar; Joseph Rayhawk; Nilanjan Mukherjee 001 (ITC, 2005)

Full-speed field programmable memory BIST supporting multi-level looping. - Xiaogang Du; Nilanjan Mukherjee 001; Wu-Tung Cheng; Sudhakar M. Reddy (MTDT, 2005)

A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops. - Xiaogang Du; Nilanjan Mukherjee 001; Chris Hill; Wu-Tung Cheng; Sudhakar M. Reddy (ATS, 2006)

X-Press Compactor for 1000x Reduction of Test Data. - Janusz Rajski; Jerzy Tyszer; Grzegorz Mrugalski; Wu-Tung Cheng; Nilanjan Mukherjee 001; Mark Kassab (ITC, 2006)

High Performance Dense Ring Generators. - Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Computers, 2006)

A RTL Testability Analyzer Based on Logical Virtual Prototyping. - Yu Huang 005; Nilanjan Mukherjee 001; Wu-Tung Cheng; Greg Aldrich (ATS, 2007)

X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. - Jerzy Tyszer; Janusz Rajski; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Mark Kassab; Wu-Tung Cheng; Manish Sharma; Liyang Lai (IEEE Des. Test Comput., 2007)

Targeting "Zero DPPM" - Can we ever get there? - Nilanjan Mukherjee 001 (DFT, 2008)

High Test Quality in Low Pin Count Applications. - Jayant D'Souza; Subramanian Mahadevan; Nilanjan Mukherjee 001; Graham Rhodes; Jocelyn Moreau; Thomas Droniou; Paul Armagnat; Damien Sartoretti (ITC, 2008)

High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST. - Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (ITC, 2008)

X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. - Janusz Rajski; Jerzy Tyszer; Grzegorz Mrugalski; Wu-Tung Cheng; Nilanjan Mukherjee 001; Mark Kassab (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Compression based on deterministic vector clustering of incompatible test cubes. - Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Dariusz Czysz; Jerzy Tyszer (ITC, 2009)

Fault diagnosis for embedded read-only memories. - Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (ITC, 2009)

High-Speed On-Chip Event Counters for Embedded Systems. - Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (VLSI Design, 2009)

Defect Aware to Power Conscious Tests - The New DFT Landscape. - Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (VLSI Design, 2009)

Highly X-Tolerant Selective Compaction of Test Responses. - Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Dariusz Czysz; Jerzy Tyszer (VTS, 2009)

Low power compression of incompatible test cubes. - Dariusz Czysz; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Przemyslaw Szczerbicki; Jerzy Tyszer (ITC, 2010)

Dynamic channel allocation for higher EDT compression in SoC designs. - Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jakub Janicki; Jerzy Tyszer (ITC, 2010)

Low capture power at-speed test in EDT environment. - Elham K. Moghaddam; Janusz Rajski; Sudhakar M. Reddy; Xijiang Lin; Nilanjan Mukherjee 001; Mark Kassab (ITC, 2010)

On Compaction Utilizing Inter and Intra-Correlation of Unknown States. - Dariusz Czysz; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

High Volume Diagnosis in Memory BIST Based on Compressed Failure Data. - Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Power Aware Embedded Test. - Xijiang Lin; Elham K. Moghaddam; Nilanjan Mukherjee 001; Benoit Nadeau-Dostie; Janusz Rajski; Jerzy Tyszer (Asian Test Symposium, 2011)

Fault Diagnosis in Memory BIST Environment with Non-march Tests. - Grzegorz Mrugalski; Artur Pogiel; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Pawel Urbanek (Asian Test Symposium, 2011)

Reduced ATE Interface for High Test Data Compression. - Dariusz Czysz; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (ETS, 2011)

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. - Jakub Janicki; Jerzy Tyszer; Avijit Dutta; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski (ITC, 2011)

Ring Generator: An Ultimate Linear Feedback Shift Register. - Nilanjan Mukherjee 001; Janusz Rajski; Grzegorz Mrugalski; Artur Pogiel; Jerzy Tyszer (Computer, 2011)

Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression. - Dariusz Czysz; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Przemyslaw Szczerbicki; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

BIST-Based Fault Diagnosis for Read-Only Memories. - Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Low power programmable PRPG with enhanced fault coverage gradient. - Jedrzej Solecki; Jerzy Tyszer; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski (ITC, 2012)

EDT Bandwidth Management in SoC Designs. - Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

New test compression scheme based on low power BIST. - Jerzy Tyszer; Michal Filipek; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski (ETS, 2013)

EDT bandwidth management - Practical scenarios for large SoC designs. - Jakub Janicki; Jerzy Tyszer; Wu-Tung Cheng; Yu Huang 005; Mark Kassab; Nilanjan Mukherjee 001; Janusz Rajski; Yan Dong; Grady Giles (ITC, 2013)

On Deploying Scan Chains for Data Storage in Test Compression Environment. - Dariusz Czysz; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Des. Test, 2013)

Test Time Reduction in EDT Bandwidth Management for SoC Designs. - Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs. - Maciej Trawka; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Jakub Janicki; Jerzy Tyszer (ATS, 2014)

On Using Implied Values in EDT-based Test Compression. - Marcin Gebala; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (DAC, 2014)

Isometric test compression with low toggling activity. - Amit Kumar 004; Mark Kassab; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Chen Wang 014 (ITC, 2014)

Innovative practices session 1C: Existing/emerging low power techniques. - Charutosh Dixit; Ramesh C. Tekumalla; Wei Zhao; Nilanjan Mukherjee 001; Vivek Chickermane (VTS, 2014)

Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs". - Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Design for low test pattern counts. - Haluk Konuk; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Deepak Solanki; Jerzy Tyszer; Justyna Zawada (DAC, 2015)

Embedded deterministic test points for compact cell-aware tests. - Cesar Acero; Derek Feltham; Friedrich Hapke; Elham K. Moghaddam; Nilanjan Mukherjee 001; Vidya Neerkundar; Marek Patyra; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (ITC, 2015)

Innovative practices session 11C: Advanced scan methodologies [3 presentations]. - Janusz Rajski; Nilanjan Mukherjee 001 (VTS, 2015)

Isometric Test Data Compression. - Amit Kumar 004; Mark Kassab; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Chen Wang 014 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. - Wu-Tung Cheng; Yan Dong; Grady Giles; Yu Huang 005; Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Low-Power Programmable PRPG With Test Compression Capabilities. - Michal Filipek; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Benoit Nadeau-Dostie; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer (IEEE Trans. Very Large Scale Integr. Syst., 2015)

On Test Points Enhancing Hardware Security. - Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (ATS, 2016)

Minimal area test points for deterministic patterns. - Yingdi Liu; Elham K. Moghaddam; Nilanjan Mukherjee 001; Sudhakar M. Reddy; Janusz Rajski; Jerzy Tyszer (ITC, 2016)

Test point insertion in hybrid test compression/LBIST architectures. - Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (ITC, 2016)

Digital Testing of ICs for Automotive Applications. - Nilanjan Mukherjee 001; Janusz Rajski (VLSID, 2016)

On New Test Points for Compact Cell-Aware Tests. - Cesar Acero; Derek Feltham; Marek Patyra; Friedrich Hapke; Elham K. Moghaddam; Nilanjan Mukherjee 001; Vidya Neerkundar; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (IEEE Des. Test, 2016)

Full-scan LBIST with capture-per-cycle hybrid test points. - Sylwester Milewski; Nilanjan Mukherjee 001; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer; Justyna Zawada (ITC, 2017)

Embedded Deterministic Test Points. - Cesar Acero; Derek Feltham; Yingdi Liu; Elham K. Moghaddam; Nilanjan Mukherjee 001; Marek Patyra; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Justyna Zawada (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Deterministic Stellar BIST for In-System Automotive Test. - Yingdi Liu; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer (ITC, 2018)

Hardware Protection via Logic Locking Test Points. - Michael Chen; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Test Time and Area Optimized BrST Scheme for Automotive ICs. - Nilanjan Mukherjee 001; Jerzy Tyszer; Daniel Tille; Mahendar Sapati; Yingdi Liu; Jeffrey Mayer; Sylwester Milewski; Elham K. Moghaddam; Janusz Rajski; Jedrzej Solecki (ITC, 2019)

Logic BIST With Capture-Per-Clock Hybrid Test Points. - Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer; Justyna Zawada (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Test Sequence-Optimized BIST for Automotive Applications. - Bartosz Kaczmarek; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Lukasz Rybak 001; Jerzy Tyszer (ETS, 2020)

X-Tolerant Tunable Compactor for In-System Test. - Yingdi Liu; Sylwester Milewski; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Bartosz Wldarczak (ITC, 2020)

Effective Design of Layout-Friendly EDT Decompressor. - Yu Huang 005; Janusz Rajski; Mark Kassab; Nilanjan Mukherjee 001; Jeffrey Mayer (VTS, 2020)

Deterministic Stellar BIST for Automotive ICs. - Yingdi Liu; Nilanjan Mukherjee 001; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Automotive Test and Reliability. - Yu Huang 005; David Francis; Yervant Zorian; Nilanjan Mukherjee 001 (ITC-Asia, 2021)

X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan. - Yingdi Liu; Sylwester Milewski; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Bartosz Wlodarczak (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Time and Area Optimized Testing of Automotive ICs. - Nilanjan Mukherjee 001; Daniel Tille; Mahendar Sapati; Yingdi Liu; Jeffrey Mayer; Sylwester Milewski; Elham K. Moghaddam; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Test Generation for an Iterative Design Flow with RTL Changes. - Jerin Joe; Nilanjan Mukherjee 001; Irith Pomeranz; Janusz Rajski (ITC, 2022)

Fast Test Generation for Structurally Similar Circuits. - Jerin Joe; Nilanjan Mukherjee 001; Irith Pomeranz; Janusz Rajski (VTS, 2022)

LBIST for Automotive ICs With Enhanced Test Generation. - Bartosz Kaczmarek; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Artur Pogiel; Janusz Rajski; Lukasz Rybak 001; Jerzy Tyszer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Innovation Practices Track: Silicon Lifecycle Management Challenges and Opportunities. - Fei Su; Xiankun Robert Jin; Nilanjan Mukherjee 001; Yervant Zorian (VTS, 2023)

Delay Monitoring Under Different PVT Corners for Test and Functional Operation. - Hari Addepalli; Jiezhong Wu; Nilanjan Mukherjee 001; Irith Pomeranz; Janusz Rajski (ITC, 2024)

Deterministic In-Fleet Scan Test for a Cloud Computing Platform. - Dan Trock; Subramanian Mahadevan; Nilanjan Mukherjee 001; Lee Harrison; Janusz Rajski; Jerzy Tyszer (ITC, 2024)

X-Tolerant Logic BIST for Automotive Designs using Observation Scan Technology. - Ashrith S. Harith; Yingdi Liu; Nilanjan Mukherjee 001; Jeffrey Mayer (VLSID, 2024)

Generation of Two-Cycle Tests for Structurally Similar Circuits. - Jerin Joe; Nilanjan Mukherjee 001; Irith Pomeranz; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

The Future of Design for Test and Silicon Lifecycle Management. - Janusz Rajski; Vivek Chickermane; Jean-François Côté; Stephan Eggersglüß; Nilanjan Mukherjee 001; Jerzy Tyszer (IEEE Des. Test, 2024)

Timing-Verification Test Generation Targeting Small Delay Defects. - Jiezhong Wu; Nilanjan Mukherjee 001; Irith Pomeranz; Kun-Han Tsai; Janusz Rajski (VTS, 2025)