Asynchronous-QDI 2D IIR digital filter circuits. - Nilanka T. Rajapaksha; Arjuna Madanayake (ISCAS, 2011)

A Row-Parallel 8 × 8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation. - Arjuna Madanayake; Renato J. Cintra; Denis Onen; Vassil S. Dimitrov; Nilanka T. Rajapaksha; Leonard T. Bruton; Amila Edirisuriya (IEEE Trans. Circuits Syst. Video Technol., 2012)

Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA. - Nilanka T. Rajapaksha; Amila Edirisuriya; Arjuna Madanayake; Renato J. Cintra; Denis Onen; Ihab Amer; Vassil S. Dimitrov (J. Electr. Comput. Eng., 2013)

A Single-Channel Architecture for Algebraic Integer-Based 8 × 8 2-D DCT Computation. - Amila Edirisuriya; Arjuna Madanayake; Renato J. Cintra; Vassil S. Dimitrov; Nilanka T. Rajapaksha (IEEE Trans. Circuits Syst. Video Technol., 2013)

2D space-time wave-digital multi-fan filter banks for signals consisting of multiple plane waves. - Nilanka T. Rajapaksha; Arjuna Madanayake; Leonard T. Bruton (Multidimens. Syst. Signal Process., 2014)

Systolic array architecture for steerable multibeam VHF wave-digital RF apertures. - Nilanka T. Rajapaksha; Arjuna Madanayake; Leonard T. Bruton (IEEE Trans. Aerosp. Electron. Syst., 2015)

VLSI Computational Architectures for the Arithmetic Cosine Transform. - Nilanka T. Rajapaksha; Arjuna Madanayake; Renato J. Cintra; Jithra Adikari; Vassil S. Dimitrov (IEEE Trans. Computers, 2015)

Fast FPGA-architecture for fan/beam-steering in wave-digital RF aperture arrays. - Sewwandi Wijayaratna; Nilanka T. Rajapaksha; Arjuna Madanayake; Len T. Bruton (Multidimens. Syst. Signal Process., 2017)

DFT Computation Using Gauss-Eisenstein Basis: FFT Algorithms and VLSI Architectures. - Diego F. G. Coelho; Renato J. Cintra; Nilanka T. Rajapaksha; Gihan J. Mendis; Arjuna Madanayake; Vassil S. Dimitrov (IEEE Trans. Computers, 2017)