Scaling towards kilo-core processors with asymmetric high-radix topologies. - Nilmini Abeyratne; Reetuparna Das; Qingkun Li; Korey Sewell; Bharan Giridhar; Ronald G. Dreslinski; David T. Blaauw; Trevor N. Mudge (HPCA, 2013)

Quality-of-Service for a High-Radix Switch. - Nilmini Abeyratne; Supreet Jeloka; Yiping Kang; David T. Blaauw; Ronald G. Dreslinski; Reetuparna Das; Trevor N. Mudge (DAC, 2014)

Enhancing DRAM Self-Refresh for Idle Power Reduction. - Byoungchan Oh; Nilmini Abeyratne; Jeongseob Ahn; Ronald G. Dreslinski; Trevor N. Mudge (ISLPED, 2016)

Checkpointing Exascale Memory Systems with Existing Memory Technologies. - Nilmini Abeyratne; Hsing Min Chen; Byoungchan Oh; Ronald G. Dreslinski; Chaitali Chakrabarti; Trevor N. Mudge (MEMSYS, 2016)

SMART: STT-MRAM architecture for smart activation and sensing. - Byoungchan Oh; Nilmini Abeyratne; Nam Sung Kim; Ronald G. Dreslinski; Trevor N. Mudge (MEMSYS, 2019)

Rethinking DRAM's Page Mode With STT-MRAM. - Byoungchan Oh; Nilmini Abeyratne; Nam Sung Kim; Jeongseob Ahn; Ronald G. Dreslinski; Trevor N. Mudge (IEEE Trans. Computers, 2023)