New algorithms for increased efficiency in hierarchical design rule checking. - Nils Hedenstierna; Kjell O. Jeppson (Integr., 1987)

CMOS Circuit Speed and Buffer Optimization. - Nils Hedenstierna; Kjell O. Jeppson (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

The use of inverse layout trees for hierarchical design verification. - Nils Hedenstierna; Kjell O. Jeppson (ICCAD, 1988)

A corner-based hierarchical circuit extractor. - Nils Hedenstierna; Kjell O. Jeppson (Integr., 1988)

The Use of Inverse Layout Trees for Hierarchical Design Rule Checking. - Nils Hedenstierna; Kjell O. Jeppson (DAC, 1989)

Comments on 'A module generator for optimized CMOS buffers'. - Nils Hedenstierna; Kjell O. Jeppson (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

The halo algorithm-an algorithm for hierarchical design of rule checking of VLSI circuits. - Nils Hedenstierna; Kjell O. Jeppson (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Formal definitions of edge-based geometric design rules. - Kjell O. Jeppson; Sven Christensson; Nils Hedenstierna (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)