Synthesis of reversible circuits with minimal lines for large functions. - Mathias Soeken; Robert Wille; Christoph Hilken; Nils Przigoda; Rolf Drechsler (ASP-DAC, 2012)

Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines. - Robert Wille; Mathias Soeken; Nils Przigoda; Rolf Drechsler (ISMVL, 2012)

A compact and efficient SAT encoding for quantum circuits. - Robert Wille; Nils Przigoda; Rolf Drechsler (AFRICON, 2013)

Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits. - Robert Wille; Mathias Soeken; Nils Przigoda; Rolf Drechsler (J. Multiple Valued Log. Soft Comput., 2013)

A generic representation of CCSL time constraints for UML/MARTE models. - Judith Peters; Robert Wille; Nils Przigoda; Ulrich Kühne; Rolf Drechsler (DAC, 2015)

Contradiction Analysis for Inconsistent Formal Models. - Nils Przigoda; Robert Wille; Rolf Drechsler (DDECS, 2015)

Verification-Driven Design Across Abstraction Levels: A Case Study. - Nils Przigoda; Jannis Stoppe; Julia Seiter 002; Robert Wille; Rolf Drechsler (DSD, 2015)

Leveraging the Analysis for Invariant Independence in Formal System Models. - Nils Przigoda; Robert Wille; Rolf Drechsler (DSD, 2015)

Verbesserung der Fehlersuche in inkonsistenten formalen Modellen (Erweiterte Zusammenfassung). - Nils Przigoda; Robert Wille; Rolf Drechsler (MBMV, 2015)

Checking concurrent behavior in UML/OCL models. - Nils Przigoda; Christoph Hilken; Robert Wille; Jan Peleska 001; Rolf Drechsler (MoDELS, 2015)

Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses. - Nils Przigoda; Judith Peters; Mathias Soeken; Robert Wille; Rolf Drechsler (MoDeVVa@MoDELS, 2015)

Towards a model-based verification methodology for Complex Swarm Systems (Invited paper). - Jonas Gomes Filho; Nils Przigoda; Robert Wille; Rolf Drechsler (ISED, 2016)

Fault Detection in Parity Preserving Reversible Circuits. - Nils Przigoda; Gerhard W. Dueck; Robert Wille; Rolf Drechsler (ISMVL, 2016)

Clocks vs. instants relations: Verifying CCSL time constraints in UML/MARTE models. - Judith Peters; Nils Przigoda; Robert Wille; Rolf Drechsler (MEMOCODE, 2016)

Frame conditions in symbolic representations of UML/OCL models. - Nils Przigoda; Jonas Gomes Filho; Philipp Niemann 001; Robert Wille; Rolf Drechsler (MEMOCODE, 2016)

Integrating an SMT-Based ModelFinder into USE. - Nils Przigoda; Frank Hilken; Judith Peters; Robert Wille; Martin Gogolla; Rolf Drechsler (MoDeVVa@MoDELS, 2016)

Ground setting properties for an efficient translation of OCL in SMT-based model finding. - Nils Przigoda; Robert Wille; Rolf Drechsler (MoDELS, 2016)

Verifying the structure and behavior in UML/OCL models using satisfiability solvers. - Nils Przigoda; Mathias Soeken; Robert Wille; Rolf Drechsler (IET Cyper-Phys. Syst.: Theory & Appl., 2016)

Analyzing Inconsistencies in UML/OCL Models. - Nils Przigoda; Robert Wille; Rolf Drechsler (J. Circuits Syst. Comput., 2016)

More than true or false: native support of irregular values in the automatic validation & verification of UML/OCL models. - Nils Przigoda; Philipp Niemann 001; Judith Peters; Frank Hilken; Robert Wille; Rolf Drechsler (MEMOCODE, 2017)

Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification. - Pablo González de Aledo; Nils Przigoda; Robert Wille; Rolf Drechsler; Pablo Sánchez Espeso (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

SMT-based validation & verification of UML-OCL models. - Nils Przigoda (2017)

Automated Validation & Verification of UML/OCL Models Using Satisfiability Solvers - Nils Przigoda; Robert Wille; Judith Przigoda; Rolf Drechsler (Springer, 2018)

Analyzing Frame Conditions in UML/OCL Models - Consistency Equivalence and Independence. - Philipp Niemann 001; Nils Przigoda; Robert Wille; Rolf Drechsler (MODELSWARD, 2018)

Generation and Validation of Frame Conditions in Formal Models. - Philipp Niemann 001; Nils Przigoda; Robert Wille; Rolf Drechsler (MODELSWARD (Revised Selected Papers), 2018)

Frame conditions in the automatic validation and verification of UML/OCL models: A symbolic formulation of modifies only statements. - Nils Przigoda; Philipp Niemann 001; Jonas Gomes Filho; Robert Wille; Rolf Drechsler (Comput. Lang. Syst. Struct., 2018)

Four-Valued Logic in UML/OCL Models: A "Playground" for the MVL Community. - Nils Przigoda; Judith Przigoda; Robert Wille (ISMVL, 2019)

Towards Automatic Design and Verification for Level 3 of the European Train Control System. - Robert Wille; Tom Peham; Judith Przigoda; Nils Przigoda (DATE, 2021)

Optimal Railway Routing Using Virtual Subsections. - Tom Peham; Judith Przigoda; Nils Przigoda; Robert Wille (RSSRail, 2022)

Coverage-Driven Test Automation for Highly-Configurable Railway Systems. - Domenik Eichhorn; Tobias Pett; Nils Przigoda; Jessica Kindsvater; Christoph Seidl 001; Ina Schaefer (VaMoS, 2023)

Design Tasks and Their Complexity for Hybrid Level 3 of the European Train Control System. - Stefan Engels; Tom Peham; Judith Przigoda; Nils Przigoda; Robert Wille (CoRR, 2023)