Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core. - Nils Wistoff; Moritz Schneider 001; Frank K. Gürkaynak; Luca Benini; Gernot Heiser (CoRR, 2020)

Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core. - Nils Wistoff; Moritz Schneider 001; Frank K. Gürkaynak; Luca Benini; Gernot Heiser (DATE, 2021)

A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. - Matteo Perotti; Matheus A. Cavalcante; Nils Wistoff; Renzo Andri; Lukas Cavigelli; Luca Benini (ASAP, 2022)

On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster. - Michael Rogenmoser; Nils Wistoff; Pirmin Vogel; Frank K. Gürkaynak; Luca Benini (ISVLSI, 2022)

Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs. - Luca Valente; Asif Veeran; Mattia Sinigaglia; Yvan Tortorella; Alessandro Nadalini; Nils Wistoff; Bruno Sá; Angelo Garofalo; Rafail Psiakis; M. Tolba; Ari Kulmala; Nimisha Limaye; et al. (HCS, 2023)

Towards a RISC-V Open Platform for Next-generation Automotive ECUs. - Luca Cuomo; Claudio Scordino; Alessandro Ottaviano; Nils Wistoff; Robert Balas; Luca Benini; Errico Guidieri; Ida Maria Savino (MECO, 2023)

AutoCC: Automatic Discovery of Covert Channels in Time-Shared Hardware. - Marcelo Orenes-Vera; Hyunsung Yun; Nils Wistoff; Gernot Heiser; Luca Benini; David Wentzlaff; Margaret Martonosi (MICRO, 2023)

Proving the Absence of Microarchitectural Timing Channels. - Scott Buckley; Robert Sison; Nils Wistoff; Curtis Millar; Toby Murray; Gerwin Klein; Gernot Heiser (CoRR, 2023)

Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning. - Nils Wistoff; Moritz Schneider 001; Frank K. Gürkaynak; Gernot Heiser; Luca Benini (IEEE Trans. Computers, 2023)

fence.t.s: Closing Timing Channels in High-Performance Out-of-Order Cores Through ISA-Supported Temporal Partitioning. - Nils Wistoff; Gernot Heiser; Luca Benini (ApplePies, 2024)

vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-Criticality Systems. - Enrico Zelioli; Alessandro Ottaviano; Robert Balas; Nils Wistoff; Angelo Garofalo; Luca Benini (ICCD, 2024)

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. - Gianna Paulin; Paul Scheffler; Thomas Benz; Matheus A. Cavalcante; Tim Fischer 001; Manuel Eggimann; Yichao Zhang 003; Nils Wistoff; Luca Bertaccini; Luca Colagrande; Gianmarco Ottavi; Frank K. Gürkaynak; et al. (VLSI Technology and Circuits, 2024)

Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor. - Riccardo Tedeschi; Luca Valente; Gianmarco Ottavi; Enrico Zelioli; Nils Wistoff; Massimiliano Giacometti; Abdul Basit Sajjad; Luca Benini; Davide Rossi (CoRR, 2024)

A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation. - Luca Valente; Alessandro Nadalini; Asif Hussain Chiralil Veeran; Mattia Sinigaglia; Bruno Sá; Nils Wistoff; Yvan Tortorella; Simone Benatti; Rafail Psiakis; Ari Kulmala; Baker Mohammad; Sandro Pinto 001; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution. - Zexin Fu; Riccardo Tedeschi; Gianmarco Ottavi; Nils Wistoff; César Fuguet; Davide Rossi; Luca Benini (CF, 2025)

AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance. - Matteo Perotti; Vincenzo Maisto; Moritz Imfeld; Nils Wistoff; Alessandro Cilardo; Luca Benini (CF (Companion), 2025)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (CoRR, 2025)

ArtistIC: An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders. - Thomas Benz; Paul Scheffler; Nils Wistoff; Philippe Sauter; Beat Muheim; Luca Benini (CoRR, 2025)

A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. - Angelo Garofalo; Alessandro Ottaviano; Matteo Perotti; Thomas Benz; Yvan Tortorella; Robert Balas; Michael Rogenmoser; Chi Zhang; Luca Bertaccini; Nils Wistoff; Maicol Ciani; Cyril Koenig; et al. (CoRR, 2025)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (IEEE J. Solid State Circuits, 2025)

CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture. - Riccardo Tedeschi; Gianmarco Ottavi; Côme Allart; Nils Wistoff; Zexin Fu; Filippo Grillotti; Fabio De Ambroggi; Elio Guidetti; Jean-Baptiste Rigaud; Olivier Potin; Jean-Roch Coulon; César Fuguet; et al. (CoRR, 2025)