A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay. - Vikas Singh; Nagendra Krishnapura; Shanthi Pavan; Baradwaj Vigraham; Nimit Nigania; Debasish Behera (CICC, 2011)

A 16 MHz BW 75 dB DR CT ΔΣ ADC Compensated for More Than One Cycle Excess Loop Delay. - Vikas Singh; Nagendra Krishnapura; Shanthi Pavan; Baradwaj Vigraham; Debasish Behera; Nimit Nigania (IEEE J. Solid State Circuits, 2012)

OpenCL Performance Evaluation on Modern Multi Core CPUs. - Joo Hwan Lee; Kaushik Patel; Nimit Nigania; Hyojong Kim; Hyesoon Kim (IPDPS Workshops, 2013)

Harmonica: An FPGA-Based Data Parallel Soft Core. - Chad D. Kersey; Sudhakar Yalamanchili; Hyojong Kim; Nimit Nigania; Hyesoon Kim (FCCM, 2014)

OpenCL Performance Evaluation on Modern Multicore CPUs. - Joo Hwan Lee; Nimit Nigania; Hyesoon Kim; Kaushik Patel; Hyojong Kim (Sci. Program., 2015)