Analysis and optimization of variable-latency designs in the presence of timing variability. - Chang-Lin Tsai; Chao-Wei Cheng; Ning-Chi Huang; Kai-Chiang Wu (DATE, 2017)

Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning Applications. - Ning-Chi Huang; Szu-Ying Chen; Kai-Chiang Wu (DATE, 2019)

Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs. - Ning-Chi Huang; Yu-Guang Chen; Kai-Chiang Wu (ISVLSI, 2019)

Fault-Tolerance Mechanism Analysis on NVDLA-Based Design Using Open Neural Network Compiler and Quantization Calibrator. - Shu-Ming Liu; Luba Tang; Ning-Chi Huang; Der-Yu Tsai; Ming-Xue Yang; Kai-Chiang Wu (VLSI-DAT, 2020)

ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design. - Samuel Liu; Jen-Ho Kuo; Luba Tang; Ning-Chi Huang; Der-Yu Tsai; M.-H. Yang; Kai-Chiang Wu (VLSI-DAT, 2021)

An Energy-Efficient Approximate Systolic Array Based on Timing Error Prediction and Prevention. - Ning-Chi Huang; Wei-Kai Tseng; Huan-Jan Chou; Kai-Chiang Wu (VTS, 2021)

Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs. - Ning-Chi Huang; Chao-Wei Cheng; Kai-Chiang Wu (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Decomposable Architecture and Fault Mitigation Methodology for Deep Learning Accelerators. - Ning-Chi Huang; Min-Syue Yang; Ya-Chu Chang; Kai-Chiang Wu (ISQED, 2023)

ELSA: Exploiting Layer-wise N: M Sparsity for Vision Transformer Acceleration. - Ning-Chi Huang; Chi-Chih Chang; Wei-Cheng Lin; Endri Taka; Diana Marculescu; Kai-Chiang Wu (CVPR Workshops, 2024)

FLORA: Fine-grained Low-Rank Architecture Search for Vision Transformer. - Chi-Chih Chang; Yuan-Yao Sung; Shixing Yu; Ning-Chi Huang; Diana Marculescu; Kai-Chiang Wu (WACV, 2024)

Palu: Compressing KV-Cache with Low-Rank Projection. - Chi-Chih Chang; Wei-Cheng Lin; Chien-Yu Lin; Chong-Yan Chen; Yu-Fang Hu; Pei-Shuo Wang; Ning-Chi Huang; Luis Ceze; Kai-Chiang Wu (CoRR, 2024)

ELSA: Exploiting Layer-wise N:M Sparsity for Vision Transformer Acceleration. - Ning-Chi Huang; Chi-Chih Chang; Wei-Cheng Lin; Endri Taka; Diana Marculescu; Kai-Chiang Wu (CoRR, 2024)

V"Mean"ba: Visual State Space Models only need 1 hidden dimension. - Tien-Yu Chi; Hung-Yueh Chiang; Chi-Chih Chang; Ning-Chi Huang; Kai-Chiang Wu (CoRR, 2024)

Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration. - Endri Taka; Ning-Chi Huang; Chi-Chih Chang; Kai-Chiang Wu; Aman Arora 001; Diana Marculescu (FPGA, 2025)

Integrating Neural Architecture Search and Rematerialization for Efficient On-Device Learning. - Chih-Ling Chen; Kai-Chiang Wu; Ning-Chi Huang (GECCO, 2025)

Palu: KV-Cache Compression with Low-Rank Projection. - Chi-Chih Chang; Wei-Cheng Lin; Chien-Yu Lin; Chong-Yan Chen; Yu-Fang Hu; Pei-Shuo Wang; Ning-Chi Huang; Luis Ceze; Mohamed S. Abdelfattah; Kai-Chiang Wu (ICLR, 2025)