Large Language Model for Verilog Generation with Golden Code Feedback. - Ning Wang 071; Bingkun Yao; Jie Zhou; Xi Wang 009; Zhe Jiang 004; Nan Guan (CoRR, 2024)

Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog. - Bingkun Yao; Ning Wang 071; Jie Zhou; Xi Wang 009; Hong Gao; Zhe Jiang 004; Nan Guan (CoRR, 2024)

UVLLM: An Automated Universal RTL Verification Framework using LLMs. - Yuchen Hu; Junhao Ye; Ke Xu; Jialin Sun; Shiyue Zhang; Xinyao Jiao; Dingrong Pan; Jie Zhou; Ning Wang 071; Weiwei Shan; Xinwei Fang; Xi Wang 009; et al. (CoRR, 2024)

Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design. - Jie Zhou; Youshu Ji; Ning Wang 071; Yuchen Hu; Xinyao Jiao; Bingkun Yao; Xinwei Fang; Shuai Zhao 004; Nan Guan; Zhe Jiang 004 (CoRR, 2025)

Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback. - Ning Wang 071; Bingkun Yao; Jie Zhou; Yuchen Hu; Xi Wang 009; Nan Guan; Zhe Jiang 004 (CoRR, 2025)

VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction. - Ning Wang 071; Bingkun Yao; Jie Zhou; Yuchen Hu; Xi Wang 009; Nan Guan; Zhe Jiang 004 (CoRR, 2025)