A novel ESD device for Whole-Chip ESD protection network of TPMS mixed signal SoC. - Ningyuan Yin; Liji Wu; Tengfei Zhai; Xiangmin Zhang; Rui Zhu (ASICON, 2013)

The write deduplication mechanism based on a novel low-power data latched sense amplifier for a magnetic tunnel junction based non-volatile memory. - Baofa Huang; Ningyuan Yin; Zhiyi Yu (ASICON, 2017)

An MTJ-Based Asynchronous System With Extremely Fine-Grained Voltage Scaling. - Ningyuan Yin; Baofa Huang; Xiaobai Chen; Jianjun Chen; Zhiyi Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

An in-memory computing multiply-and-accumulate circuit based on ternary STT-MRAMs for convolutional neural networks. - Guihua Zhao; Xing Jin 005; Huafeng Ye; Yating Peng; Wei Liu; Ningyuan Yin; Weichong Chen; Jianjun Chen; Ximing Li 003; Zhiyi Yu (IEICE Electron. Express, 2022)

A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations. - Xing Jin 005; Ningyuan Yin; Weichong Chen; Ximing Li 003; Guihua Zhao; Zhiyi Yu (IEICE Electron. Express, 2023)

High-Reliability, Reconfigurable, and Fully Non-volatile Full-Adder Based on SOT-MTJ for Image Processing Applications. - Xing Jin 005; Weichong Chen; Ximing Li 003; Ningyuan Yin; Caihua Wan; Mingkun Zhao; Xiufeng Han; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Parallel-Prefix Adder in Spin-Orbit Torque Magnetic RAM for High Bit-Width Non-Volatile Computation. - Ximing Li 003; Xing Jin 005; Weichong Chen; Ningyuan Yin; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style. - Wanyuan Pan; Yihe Yu; Chengcheng Tang; Ningyuan Yin; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

FDAIMC: A Fully-Differential Analog In-Memory-Computing for MAC in MRAM with Accuracy Calibration Under Process and Voltage Variation. - Xiangyu Li; Weichong Chen; Ruida Hong; Jinghai Wang; Ningyuan Yin; Zhiyi Yu (DATE, 2025)