Design of Testable CMOS Logic Circuits Under Arbitrary Delays. - Niraj K. Jha; Jacob A. Abraham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985)

Detecting Multiple Faults in CMOS Circuits. - Niraj K. Jha (ITC, 1986)

On the design of robust multiple fault testable CMOS combinational logic circuits. - Sandip Kundu; Sudhakar M. Reddy; Niraj K. Jha (ICCAD, 1988)

A new class of symmetric error correcting / unidirectional error detecting codes. - Niraj K. Jha (ICCD, 1988)

Multiple Stuck-Open Fault Detection in CMOS Logic Circuits. - Niraj K. Jha (IEEE Trans. Computers, 1988)

A universal test set for CMOS circuits. - Gopal Gupta 001; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Testing for multiple faults in domino-CMOS logic circuits. - Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Fault detection in CVS parity trees: application in SSC CVS parity and two-rail checkers. - Niraj K. Jha (FTCS, 1989)

Design of sufficiently strongly self-checking embedded checkers for systematic and separable codes. - Niraj K. Jha (ICCD, 1989)

Separable codes for detecting unidirectional errors. - Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

A totally self-checking checker for Borden's code. - Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Comments on 'A MOS implementation of totally self-checking checker for the 1-out-of-3 code'. - Niraj K. Jha (IEEE J. Solid State Circuits, 1989)

Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring. - Niraj K. Jha; Qiao Tong (EURO-DAC, 1990)

A dependence graph-based approach to the design of algorithm-based fault tolerant systems. - Bapiraju Vinnakota; Niraj K. Jha (FTCS, 1990)

Design of robustly testable static CMOS parity trees derived from binary decision diagrams. - Niraj K. Jha; Carol Q. Tong (ICCD, 1990)

Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits. - Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Testing of differential cascode voltage switch one-count generators. - Niraj K. Jha (IEEE J. Solid State Circuits, 1990)

Testing of multiple-output domino logic (MODL) CMOS circuits. - Niraj K. Jha; Qiao Tong (IEEE J. Solid State Circuits, 1990)

Testing of zipper CMOS logic circuits. - Qiao Tong; Niraj K. Jha (IEEE J. Solid State Circuits, 1990)

MACHETE: synthesis of sequential machines for easy testability. - Bapiraju Vinnakota; Niraj K. Jha (EURO-DAC, 1991)

Design of Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. - Bapiraju Vinnakota; Niraj K. Jha (FTCS, 1991)

Design and Synthesis of Self-Checking VLSI Circuits and Systems. - Niraj K. Jha; Sying-Jyan Wang (ICCD, 1991)

Optimal Design of Checks for Error Detection and Location in Fault Tolerant Multiprocessors Systems. - Ramesh K. Sitaraman; Niraj K. Jha (Fault-Tolerant Computing Systems, 1991)

A new transition count method for testing of logic circuits. - Konstantinos I. Diamantaras; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Totally self-checking checker designs for Bose-Lin, Bose, and Blaum codes. - Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Design of robustly testable combinational logic circuits. - Sandip Kundu; Sudhakar M. Reddy; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Easily testable gate-level and DCVS multipliers. - Andres R. Takach; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Design of C-testable DCVS binary array dividers. - Qiao Tong; Niraj K. Jha (IEEE J. Solid State Circuits, 1991)

Robustly testable static CMOS parity trees derived from binary decision diagrams. - Niraj K. Jha; Qiao Tong (IEEE J. Solid State Circuits, 1991)

Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability. - Niraj K. Jha; Irith Pomeranz; Sudhakar M. Reddy; Robert J. Miller (FTCS, 1992)

Behavioral synthesis for easy testability in data path scheduling. - Tien-Chien Lee; Wayne H. Wolf; Niraj K. Jha (ICCAD, 1992)

Multiple Input Bridging Fault Detection in CMOS Sequential Circuits. - Niraj K. Jha; Sying-Jyan Wang; Phillip C. Gripka (ICCD, 1992)

Behavioral Synthesis for Easy Testability in Data Path Allocation. - Tien-Chien Lee; Wayne H. Wolf; Niraj K. Jha; John M. Acken (ICCD, 1992)

Design and Analysis of Fault-Detecting and Fault-Locating Schedules for Computation DAGs. - Shalini Yajnik; Niraj K. Jha (IPPS, 1992)

Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments. - Tien-Chien Lee; Niraj K. Jha; Wayne H. Wolf (DAC, 1993)

Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial Scan. - Sandeep Bhatia; Niraj K. Jha (ICCD, 1993)

Efficient Diagnosis in Algorithm-Based Fault Tolerant Multiprocessor Systems. - Santhanam Srinivasan; Niraj K. Jha (ICCD, 1993)

Design of Algorithm-Based Fault Tolerant Systems With In-System Checks. - Shalini Yajnik; Niraj K. Jha (ICPP (1), 1993)

A Conditional Resource-Sharing Method for Behavior Synthesis of Highly- Testable Data Paths. - Tien-Chien Lee; Niraj K. Jha; Wayne H. Wolf (ITC, 1993)

Synthesis of Sequential Circuits for Robust Path Delay Fault Testability. - Sandeep Bhatia; Niraj K. Jha (VLSI Design, 1993)

Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers. - Niraj K. Jha (IEEE Trans. Computers, 1993)

Optimal Design of Checks for Error Detection and Location in Fault-Tolerant Multiprocessor Systems. - Ramesh K. Sitaraman; Niraj K. Jha (IEEE Trans. Computers, 1993)

Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems. - Bapiraju Vinnakota; Niraj K. Jha (IEEE Trans. Computers, 1993)

Easily testable nonrestoring and restoring gate-level cellular array dividers. - Niraj K. Jha; Abha Ahuja (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Design and synthesis of self-checking VLSI circuits. - Niraj K. Jha; Sying-Jyan Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs. - Bapiraju Vinnakota; Niraj K. Jha (IEEE Trans. Parallel Distributed Syst., 1993)

Genesis: A Behavioral Synthesis System for Hierarchical Testability. - Sandeep Bhatia; Niraj K. Jha (EDAC-ETC-EUROASIC, 1994)

Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches. - Sandeep Bhatia; Niraj K. Jha (ICCD, 1994)

Behavioral Synthesis for low Power. - Anand Raghunathan; Niraj K. Jha (ICCD, 1994)

Synthesis of Fault Tolerant Architectures for Molecular Dynamics. - Shalini Yajnik; Niraj K. Jha (ISCAS, 1994)

A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme. - Steven W. Burns; Niraj K. Jha (IEEE Trans. Computers, 1994)

Algorithm-Based Fault Tolerance for FFT Networks. - Sying-Jyan Wang; Niraj K. Jha (IEEE Trans. Computers, 1994)

Partitioned Encoding Schemes for Algorithm-Based Fault Tolerance in Massively Parallel Systems. - Jennifer Rexford; Niraj K. Jha (IEEE Trans. Parallel Distributed Syst., 1994)

Design of Algorithm-Based Fault-Tolerant Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. - Bapiraju Vinnakota; Niraj K. Jha (IEEE Trans. Parallel Distributed Syst., 1994)

Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems. - Santhanam Srinivasan; Niraj K. Jha (EURO-DAC, 1995)

An iterative improvement algorithm for low power data path synthesis. - Anand Raghunathan; Niraj K. Jha (ICCAD, 1995)

Task Allocation for Safety and Reliability in Distributed Systems. - Santhanam Srinivasan; Niraj K. Jha (ICPP (2), 1995)

An ILP Formulation for Low Power Based on Minimizing Switched Capacitance During Data Path Allocation. - Anand Raghunathan; Niraj K. Jha (ISCAS, 1995)

Glitch Analysis and Reduction in Register Transfer Level. - Anand Raghunathan; Sujit Dey; Niraj K. Jha (DAC, 1996)

Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis. - Ganesh Lakshminarayana; Anand Raghunathan; Niraj K. Jha (FTCS, 1996)

A design for testability technique for RTL circuits using control/data flow extraction. - Indradeep Ghosh; Anand Raghunathan; Niraj K. Jha (ICCAD, 1996)

Register-transfer level estimation techniques for switching activity and power consumption. - Anand Raghunathan; Sujit Dey; Niraj K. Jha (ICCAD, 1996)

Controller re-specification to minimize switching activity in controller/data path circuits. - Anand Raghunathan; Sujit Dey; Niraj K. Jha; Kazutoshi Wakabayashi (ISLPED, 1996)

Hardware-Software Co-Design for Test: It's the Last Straw! - J. El-Ziq; Najmi T. Jarwala; Niraj K. Jha; Peter Marwedel; Christos A. Papachristou; Janusz Rajski; John W. Sheppard (VTS, 1996)

Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability. - Sandeep Bhatia; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

COSYN: Hardware-Software Co-Synthesis of Embedded Systems. - Bharat P. Dave; Ganesh Lakshminarayana; Niraj K. Jha (DAC, 1997)

Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. - Indradeep Ghosh; Anand Raghunathan; Niraj K. Jha (DAC, 1997)

Power Management Techniques for Control-Flow Intensive Designs. - Anand Raghunathan; Sujit Dey; Niraj K. Jha; Kazutoshi Wakabayashi (DAC, 1997)

COFTA: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded System Architectures for Low Overhead Fault Tolerance. - Bharat P. Dave; Niraj K. Jha (FTCS, 1997)

MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems. - Robert P. Dick; Niraj K. Jha (ICCAD, 1997)

Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions. - Ganesh Lakshminarayana; Kamal S. Khouri; Niraj K. Jha (ICCAD, 1997)

A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems. - Indradeep Ghosh; Niraj K. Jha; Sujit Dey (ITC, 1997)

Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. - Indradeep Ghosh; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. - Steven M. Nowick; Niraj K. Jha; Fu-Chiung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

SCALP: an iterative-improvement-based low-power data path synthesis system. - Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Analysis and Randomized Design of Algorithm-Based Fault Tolerant Multiprocessor Systems Under an Extended Model. - Shalini Yajnik; Niraj K. Jha (IEEE Trans. Parallel Distributed Syst., 1997)

Graceful Degradation in Algorithm-Based Fault Tolerant Multiprocessor Systems. - Shalini Yajnik; Niraj K. Jha (IEEE Trans. Parallel Distributed Syst., 1997)

High-Level Power Analysis and Optimization. - Anand Raghunathan; Niraj K. Jha; Sujit Dey (Kluwer, 1998)

A Fast and Low Cost Testing Technique for Core-Based System-on-Chip. - Indradeep Ghosh; Sujit Dey; Niraj K. Jha (DAC, 1998)

A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis. - Indradeep Ghosh; Niraj K. Jha; Sudipta Bhawmik (DAC, 1998)

FACT: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions. - Ganesh Lakshminarayana; Niraj K. Jha (DAC, 1998)

Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions. - Ganesh Lakshminarayana; Niraj K. Jha (DAC, 1998)

Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions. - Ganesh Lakshminarayana; Anand Raghunathan; Niraj K. Jha (DAC, 1998)

CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures. - Bharat P. Dave; Niraj K. Jha (DATE, 1998)

IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits. - Kamal S. Khouri; Ganesh Lakshminarayana; Niraj K. Jha (DATE, 1998)

CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems. - Robert P. Dick; Niraj K. Jha (ICCAD, 1998)

Transforming control-flow intensive designs to facilitate power management. - Ganesh Lakshminarayana; Anand Raghunathan; Niraj K. Jha; Sujit Dey (ICCAD, 1998)

Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions. - Srivaths Ravi 001; Ganesh Lakshminarayana; Niraj K. Jha (ICCAD, 1998)

Fast high-level power estimation for control-flow intensive design. - Kamal S. Khouri; Ganesh Lakshminarayana; Niraj K. Jha (ISLPED, 1998)

TAO: regular expression based high-level testability analysis and optimization. - Srivaths Ravi 001; Ganesh Lakshminarayana; Niraj K. Jha (ITC, 1998)

COHRA: Hardware-Software Co-Synthesis of Hierarchical Distributed Embedded System Architectures. - Bharat P. Dave; Niraj K. Jha (VLSI Design, 1998)

A Power Management Methodology for High-Level Synthesis. - Ganesh Lakshminarayana; Anand Raghunathan; Niraj K. Jha; Sujit Dey (VLSI Design, 1998)

Guest Editorial. - Niraj K. Jha (J. Electron. Test., 1998)

High-level test synthesis: a survey. - Indradeep Ghosh; Niraj K. Jha (Integr., 1998)

COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems. - Bharat P. Dave; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems. - Robert P. Dick; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

A design-for-testability technique for register-transfer level circuits using control/data flow extraction. - Indradeep Ghosh; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits. - Sandeep Bhatia; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Common-Case Computation: A High-Level Technique for Power and Performance Optimization. - Ganesh Lakshminarayana; Anand Raghunathan; Kamal S. Khouri; Niraj K. Jha; Sujit Dey (DAC, 1999)

MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis. - Robert P. Dick; Niraj K. Jha (DATE, 1999)

Memory binding for performance optimization of control-flow intensive behaviors. - Kamal S. Khouri; Ganesh Lakshminarayana; Niraj K. Jha (ICCAD, 1999)

A framework for testing core-based systems-on-a-chip. - Srivaths Ravi 001; Ganesh Lakshminarayana; Niraj K. Jha (ICCAD, 1999)

TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. - Srivaths Ravi 001; Ganesh Lakshminarayana; Niraj K. Jha (VTS, 1999)

COFTA: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded Systems. - Bharat P. Dave; Niraj K. Jha (IEEE Trans. Computers, 1999)

Controller-based power management for control-flow intensive designs. - Sujit Dey; Anand Raghunathan; Niraj K. Jha; Kazutoshi Wakabayashi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Corrections to "mogac: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems". - Robert P. Dick; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

A low overhead design for testability and test generation technique for core-based systems-on-a-chip. - Indradeep Ghosh; Niraj K. Jha; Sujit Dey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Hierarchical test generation and design for testability methods for ASPPs and ASIPs. - Indradeep Ghosh; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

High-level synthesis of low-power control-flow intensive circuits. - Kamal S. Khouri; Ganesh Lakshminarayana; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors. - Ganesh Lakshminarayana; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions. - Ganesh Lakshminarayana; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Wavesched: a novel scheduling technique for control-flow intensive designs. - Ganesh Lakshminarayana; Kamal S. Khouri; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Register transfer level power optimization with emphasis on glitch analysis and reduction. - Anand Raghunathan; Sujit Dey; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Safety and Reliability Driven Task Allocation in Distributed Systems. - Santhanam Srinivasan; Niraj K. Jha (IEEE Trans. Parallel Distributed Syst., 1999)

COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems. - Bharat P. Dave; Ganesh Lakshminarayana; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Power management in high-level synthesis. - Ganesh Lakshminarayana; Anand Raghunathan; Niraj K. Jha; Sujit Dey (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Power analysis of embedded operating systems. - Robert P. Dick; Ganesh Lakshminarayana; Anand Raghunathan; Niraj K. Jha (DAC, 2000)

Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems. - Jiong Luo; Niraj K. Jha (ICCAD, 2000)

A Technique for Identifying RTL and Gate-Level Correspondences. - Srivaths Ravi 001; Niraj K. Jha; Indradeep Ghosh; Vamsi Boppana (ICCD, 2000)

: Reducing test application time in high-level test generation. - Srivaths Ravi 001; Ganesh Lakshminarayana; Niraj K. Jha (ITC, 2000)

COWLS: Hardware-Software Co-Synthesis of Distributed Wireless Low-Power Embedded Client-Server Systems. - Robert P. Dick; Niraj K. Jha (VLSI Design, 2000)

Clock Selection for Performance Optimization of Control-Flow Intensive Behaviors. - Kamal S. Khouri; Niraj K. Jha (VLSI Design, 2000)

Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis. - Ganesh Lakshminarayana; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Computers, 2000)

A fast and low-cost testing technique for core-based system-chips. - Indradeep Ghosh; Sujit Dey; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

A BIST scheme for RTL circuits based on symbolic testabilityanalysis. - Indradeep Ghosh; Niraj K. Jha; Sudipta Bhawmik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs. - Ganesh Lakshminarayana; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. - Srivaths Ravi 001; Ganesh Lakshminarayana; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems. - Jiong Luo; Niraj K. Jha (DAC, 2001)

High-level Software Energy Macro-modeling. - Tat Kee Tan; Anand Raghunathan; Ganesh Lakshminarayana; Niraj K. Jha (DAC, 2001)

Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization. - Weidong Wang; Anand Raghunathan; Ganesh Lakshminarayana; Niraj K. Jha (DAC, 2001)

Low Power System Scheduling and Synthesis. - Niraj K. Jha (ICCAD, 2001)

High-Level Power Modeling of CPLDs and FPGAs. - Li Shang; Niraj K. Jha (ICCD, 2001)

Fast test generation for circuits with RTL and gate-level views. - Srivaths Ravi 001; Niraj K. Jha (ITC, 2001)

Synthesis of System-on-a-chip for Testability. - Srivaths Ravi 001; Niraj K. Jha (VLSI Design, 2001)

Clock selection for performance optimization of control-flowintensive behaviors. - Kamal S. Khouri; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. - Srivaths Ravi 001; Indradeep Ghosh; Vamsi Boppana; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Testing of core-based systems-on-a-chip. - Srivaths Ravi 001; Ganesh Lakshminarayana; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

TAO: regular expression-based register-transfer level testability analysis and optimization. - Srivaths Ravi 001; Ganesh Lakshminarayana; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis. - Jiong Luo; Niraj K. Jha (HiPC, 2002)

High-level synthesis of distributed logic-memory architectures. - Chao Huang; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (ICCAD, 2002)

Synthesis of custom processors based on extensible platforms. - Fei Sun; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (ICCAD, 2002)

Interconnect-aware high-level synthesis for low power. - Lin Zhong 001; Niraj K. Jha (ICCAD, 2002)

Embedded Operating System Energy Analysis and Macro-Modeling. - Tat Kee Tan; Anand Raghunathan; Niraj K. Jha (ICCD, 2002)

Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors. - Lin Zhong 001; Jiong Luo; Yunsi Fei; Niraj K. Jha (ICCD, 2002)

Task graph transformation to aid system synthesis. - Keith S. Vallerio; Niraj K. Jha (ISCAS (4), 2002)

An Economics-based Power-aware Protocol for Computation Distribution in Mobile Ad-Hoc Networks. - Li Shang; Robert P. Dick; Niraj K. Jha (IASTED PDCS, 2002)

Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip. - Yunsi Fei; Niraj K. Jha (ASP-DAC/VLSI Design, 2002)

Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems. - Jiong Luo; Niraj K. Jha (ASP-DAC/VLSI Design, 2002)

Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs. - Li Shang; Niraj K. Jha (ASP-DAC/VLSI Design, 2002)

Input Space Adaptive Embedded Software Synthesis. - Weidong Wang; Anand Raghunathan; Ganesh Lakshminarayana; Niraj K. Jha (ASP-DAC/VLSI Design, 2002)

Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links. - Li Shang; Li-Shiuan Peh; Niraj K. Jha (IEEE Comput. Archit. Lett., 2002)

Test synthesis of systems-on-a-chip. - Srivaths Ravi 001; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

High-level test compaction techniques. - Srivaths Ravi 001; Ganesh Lakshminarayana; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

High-level energy macromodeling of embedded software. - Tat Kee Tan; Anand Raghunathan; Ganesh Lakshminarayana; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Leakage power analysis and reduction during behavioral synthesis. - Kamal S. Khouri; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Software Architectural Transformations. - Tat Kee Tan; Anand Raghunathan; Niraj K. Jha (Embedded Software for SoC, 2003)

Graphical user interface energy characterization for handheld computers. - Lin Zhong 001; Niraj K. Jha (CASES, 2003)

Energy Estimation for Extensible Processors. - Yunsi Fei; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (DATE, 2003)

Software Architectural Transformations: A New Approach to Low Energy Embedded Software. - Tat Kee Tan; Anand Raghunathan; Niraj K. Jha (DATE, 2003)

A comprehensive high-level synthesis system for control-flow intensive behaviors. - Weidong Wang; Tat Kee Tan; Jiong Luo; Yunsi Fei; Li Shang; Keith S. Vallerio; Lin Zhong 001; Anand Raghunathan; Niraj K. Jha (ACM Great Lakes Symposium on VLSI, 2003)

Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. - Li Shang; Li-Shiuan Peh; Niraj K. Jha (HPCA, 2003)

A High-level Interconnect Power Model for Design Space Exploration. - Pallav Gupta; Lin Zhong 001; Niraj K. Jha (ICCAD, 2003)

Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications. - Chao Huang; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (ICCAD, 2003)

A Scalable Application-Specific Processor Synthesis Methodology. - Fei Sun; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (ICCAD, 2003)

Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems. - Le Yan; Jiong Luo; Niraj K. Jha (ICCAD, 2003)

Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. - Loganathan Lingappan; Srivaths Ravi 001; Niraj K. Jha (ICCD, 2003)

PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks. - Li Shang; Li-Shiuan Peh; Niraj K. Jha (ICS, 2003)

Analyzing the energy consumption of security protocols. - Nachiketh R. Potlapally; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (ISLPED, 2003)

Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems. - Jiong Luo; Niraj K. Jha (VLSI Design, 2003)

Task Graph Extraction for Embedded System Synthesis. - Keith S. Vallerio; Niraj K. Jha (VLSI Design, 2003)

High-level Synthesis of Multi-process Behavioral Descriptions. - Weidong Wang; Niraj K. Jha; Anand Raghunathan; Sujit Dey (VLSI Design, 2003)

Analysis of power dissipation in embedded systems using real-time operating systems. - Robert P. Dick; Ganesh Lakshminarayana; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

A simulation framework for energy-consumption analysis of OS-driven embedded applications. - Tat Kee Tan; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

High-level macro-modeling and estimation techniques for switching activity and power consumption. - Anand Raghunathan; Sujit Dey; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2003)

An Energy-Aware Synthesis Methodology for OS-Driven Multi-Process Embedded Software. - Tat Kee Tan; Anand Raghunathan; Niraj K. Jha (ESA/VLSI, 2004)

Evaluating Conditional Statements in Embedded System Software: Systematic Methodologies for Reducing Energy Consumption. - Keith S. Vallerio; Niraj K. Jha (ESA/VLSI, 2004)

Language Selection for Mobile Systems: Java, C, or Both? - Keith S. Vallerio; Niraj K. Jha (ESA/VLSI, 2004)

Synthesis of Reversible Logic. - Abhinav Agrawal 002; Niraj K. Jha (DATE, 2004)

An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology. - Pallav Gupta; Niraj K. Jha (DATE, 2004)

Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies. - Rui Zhang; Pallav Gupta; Lin Zhong 001; Niraj K. Jha (DATE, 2004)

High-level synthesis using computation-unit integrated memories. - Chao Huang; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (ICCAD, 2004)

Power estimation for cycle-accurate functional descriptions of hardware. - Lin Zhong 001; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (ICCAD, 2004)

An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks. - Pallav Gupta; Rui Zhang; Niraj K. Jha (ICCD, 2004)

An Energy-Aware Framework for Coordinated Dynamic Software Management in Mobile Computers. - Yunsi Fei; Lin Zhong 001; Niraj K. Jha (MASCOTS, 2004)

Thermal Modeling, Characterization and Management of On-Chip Networks. - Li Shang; Li-Shiuan Peh; Amit Kumar 002; Niraj K. Jha (MICRO, 2004)

Energy-Optimizing Source Code Transformations for OS-driven Embedded Software. - Yunsi Fei; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (VLSI Design, 2004)

Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization. - Weidong Wang; Anand Raghunathan; Niraj K. Jha (VLSI Design, 2004)

Dynamic Power Optimization of Interactive Systems. - Lin Zhong 001; Niraj K. Jha (VLSI Design, 2004)

COWLS: hardware-software cosynthesis of wireless low-power distributed embedded client-server systems. - Robert P. Dick; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

A hybrid energy-estimation technique for extensible processors. - Yunsi Fei; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Common-case computation: a high-level energy and performance optimization technique. - Ganesh Lakshminarayana; Anand Raghunathan; Kamal S. Khouri; Niraj K. Jha; Sujit Dey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Register binding-based RTL power management for control-flow intensive designs. - Jiong Luo; Lin Zhong 001; Yunsi Fei; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Custom-instruction synthesis for extensible-processor platforms. - Fei Sun; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Resource budgeting for Multiprocess High-level synthesis. - Weidong Wang; Anand Raghunathan; Niraj K. Jha; Sujit Dey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

DESP: A Distributed Economics-Based Subcontracting Protocol for Computation Distribution in Power-Aware Mobile Ad Hoc Networks. - Li Shang; Robert P. Dick; Niraj K. Jha (IEEE Trans. Mob. Comput., 2004)

Input space adaptive design: a high-level methodology for optimizing energy and performance. - Weidong Wang; Anand Raghunathan; Ganesh Lakshminarayana; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory. - Chao Huang; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (CICC, 2005)

Enhancing security through hardware-assisted run-time validation of program data properties. - Divya Arora 001; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha (CODES+ISSS, 2005)

Efficient fingerprint-based user authentication for embedded systems. - Pallav Gupta; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (DAC, 2005)

Hybrid simulation for embedded software energy estimation. - Anish Muttreja; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha (DAC, 2005)

User-perceived latency driven voltage scaling for interactive applications. - Le Yan; Lin Zhong 001; Niraj K. Jha (DAC, 2005)

Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. - Divya Arora 001; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (DATE, 2005)

Nanotechnology in the Service of Embedded and Ubiquitous Computing. - Niraj K. Jha (EUC, 2005)

ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology. - Wei Zhang 012; Niraj K. Jha (ICCD, 2005)

Towards a Responsive, Yet Power-ef.cient, Operating System: A Holistic Approach. - Le Yan; Lin Zhong 001; Niraj K. Jha (MASCOTS, 2005)

A personal-area network of low-power wireless interfacing devices for handhelds: system and hardware design. - Lin Zhong 001; Mike Sinclair; Niraj K. Jha (Mobile HCI, 2005)

Energy efficiency of handheld computer interfaces: limits, characterization and practice. - Lin Zhong 001; Niraj K. Jha (MobiSys, 2005)

Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. - Loganathan Lingappan; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha; Srimat T. Chakradhar (VLSI Design, 2005)

Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. - Fei Sun; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (VLSI Design, 2005)

Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies. - Rui Zhang; Pallav Gupta; Niraj K. Jha (VLSI Design, 2005)

Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits. - Loganathan Lingappan; Niraj K. Jha (VTS, 2005)

Integrated functional partitioning and synthesis for low power distributed systems of systems-on-a-chip. - Yunsi Fei; Niraj K. Jha (Int. J. Embed. Syst., 2005)

Generation of distributed logic-memory architectures through high-level synthesis. - Chao Huang; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Input space-adaptive optimization for embedded-software synthesis. - Weidong Wang; Anand Raghunathan; Ganesh Lakshminarayana; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems. - Le Yan; Jiong Luo; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Threshold network synthesis and optimization and its application to nanotechnologies. - Rui Zhang; Pallav Gupta; Lin Zhong 001; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Interconnect-aware low-power high-level synthesis. - Lin Zhong 001; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Energy macromodeling of embedded operating systems. - Tat Kee Tan; Anand Raghunathan; Niraj K. Jha (ACM Trans. Embed. Comput. Syst., 2005)

Memory binding for performance optimization of control-flow intensive behavioral descriptions. - Kamal S. Khouri; Ganesh Lakshminarayana; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Architectural support for safe software execution on embedded processors. - Divya Arora 001; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha (CODES+ISSS, 2006)

Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. - Divya Arora 001; Anand Raghunathan; Srivaths Ravi 001; Murugan Sankaradass; Niraj K. Jha; Srimat T. Chakradhar (DAC, 2006)

HybDTM: a coordinated hardware-software approach for dynamic thermal management. - Amit Kumar 002; Li Shang; Li-Shiuan Peh; Niraj K. Jha (DAC, 2006)

NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture. - Wei Zhang 012; Niraj K. Jha; Li Shang (DAC, 2006)

Architectures for efficient face authentication in embedded systems. - Najwa Aaraj; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (DATE Designers' Forum, 2006)

Test generation for combinational quantum cellular automata (QCA) circuits. - Pallav Gupta; Niraj K. Jha; Loganathan Lingappan (DATE, 2006)

Satisfiability-based framework for enabling side-channel attacks on cryptographic software. - Nachiketh R. Potlapally; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha; Ruby B. Lee (DATE Designers' Forum, 2006)

Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations. - Rui Zhang; Niraj K. Jha (ACM Great Lakes Symposium on VLSI, 2006)

Active Learning Driven Data Acquisition for Sensor Networks. - Anish Muttreja; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha (ISCC, 2006)

Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults. - Loganathan Lingappan; Niraj K. Jha (VLSI Design, 2006)

Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. - Nachiketh R. Potlapally; Srivaths Ravi 001; Anand Raghunathan; Ruby B. Lee; Niraj K. Jha (VLSI Design, 2006)

Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. - Fei Sun; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (VLSI Design, 2006)

State Encoding of Finite-State Machines Targeting Threshold and Majority Logic Based Implementations with Application to Nanotechnologies. - Rui Zhang; Niraj K. Jha (VLSI Design, 2006)

Temperature-Aware On-Chip Networks. - Li Shang; Li-Shiuan Peh; Amit Kumar 002; Niraj K. Jha (IEEE Micro, 2006)

An Algorithm for Synthesis of Reversible Logic Circuits. - Pallav Gupta; Abhinav Agrawal 002; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Use of Computation-Unit Integrated Memories in High-Level Synthesis. - Chao Huang; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Satisfiability-based test generation for nonseparable RTL controller-datapath circuits. - Loganathan Lingappan; Srivaths Ravi 001; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. - Loganathan Lingappan; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha; Srimat T. Chakradhar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks. - Li Shang; Li-Shiuan Peh; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Application-specific heterogeneous multiprocessor synthesis using extensible processors. - Fei Sun; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

RTL-Aware Cycle-Accurate Functional Power Estimation. - Lin Zhong 001; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols. - Nachiketh R. Potlapally; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Mob. Comput., 2006)

Energy-Efficient Graphical User Interface Design. - Keith S. Vallerio; Lin Zhong 001; Niraj K. Jha (IEEE Trans. Mob. Comput., 2006)

Dynamic Power Optimization Targeting User Delays in Interactive Systems. - Lin Zhong 001; Niraj K. Jha (IEEE Trans. Mob. Comput., 2006)

Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors. - Divya Arora 001; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A Scalable Synthesis Methodology for Application-Specific Processors. - Fei Sun; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Energy comparison and optimization of wireless body-area network technologies. - Le Yan; Lin Zhong 001; Niraj K. Jha (BODYNETS, 2007)

NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture. - Wei Zhang 012; Li Shang; Niraj K. Jha (DAC, 2007)

Energy and execution time analysis of a software-based trusted platform module. - Najwa Aaraj; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha (DATE, 2007)

A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS. - Amit Kumar 002; Partha Kundu; Arvind P. Singh; Li-Shiuan Peh; Niraj K. Jha (ICCD, 2007)

CMOS logic design with independent-gate FinFETs. - Anish Muttreja; Niket Agarwal; Niraj K. Jha (ICCD, 2007)

Express virtual channels: towards the ideal interconnection fabric. - Amit Kumar 002; Li-Shiuan Peh; Partha Kundu; Niraj K. Jha (ISCA, 2007)

Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits. - Loganathan Lingappan; Vijay Gangaram; Niraj K. Jha (VLSI Design, 2007)

Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits. - Loganathan Lingappan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Power-Efficient Scheduling for Heterogeneous Distributed Real-Time Embedded Systems. - Jiong Luo; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Automated Energy/Performance Macromodeling of Embedded Software. - Anish Muttreja; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Hybrid Simulation for Energy Estimation of Embedded Software. - Anish Muttreja; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

SLOPES: Hardware-Software Cosynthesis of Low-Power Real-Time Distributed Embedded Systems With Dynamically Reconfigurable FPGAs. - Li Shang; Robert P. Dick; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors. - Fei Sun; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies. - Rui Zhang; Pallav Gupta; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Energy-optimizing source code transformations for operating system-driven embedded software. - Yunsi Fei; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (ACM Trans. Embed. Comput. Syst., 2007)

Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems. - Najwa Aaraj; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Architectural Support for Run-Time Validation of Program Data Properties. - Divya Arora 001; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. - Divya Arora 001; Anand Raghunathan; Srivaths Ravi 001; Murugan Sankaradass; Niraj K. Jha; Srimat T. Chakradhar (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A Test Generation Framework for Quantum Cellular Automata Circuits. - Pallav Gupta; Niraj K. Jha; Loganathan Lingappan (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. - Chao Huang; Srivaths Ravi 001; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Editorial. - Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors. - Loganathan Lingappan; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. - Jiong Luo; Niraj K. Jha; Li-Shiuan Peh (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis. - Nachiketh R. Potlapally; Anand Raghunathan; Srivaths Ravi 001; Niraj K. Jha; Ruby B. Lee (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. - Nachiketh R. Potlapally; Srivaths Ravi 001; Anand Raghunathan; Ruby B. Lee; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Dynamic Binary Instrumentation-Based Framework for Malware Defense. - Najwa Aaraj; Anand Raghunathan; Niraj K. Jha (DIMVA, 2008)

A system-level perspective for efficient NoC design. - Amit Kumar 002; Niket Agarwal; Li-Shiuan Peh; Niraj K. Jha (IPDPS, 2008)

Token flow control. - Amit Kumar 002; Li-Shiuan Peh; Niraj K. Jha (MICRO, 2008)

Evaluation of multiple supply and threshold voltages for low-power FinFET circuit synthesis. - Prateek Mishra; Anish Muttreja; Niraj K. Jha (NANOARCH, 2008)

Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects. - Anish Muttreja; Prateek Mishra; Niraj K. Jha (VLSI Design, 2008)

Variability-Tolerant Register-Transfer Level Synthesis. - Anish Muttreja; Srivaths Ravi 001; Niraj K. Jha (VLSI Design, 2008)

Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture. - Muzaffer O. Simsir; Srihari Cadambi; Franjo Ivancic; Martin Rötteler; Niraj K. Jha (VLSI Design, 2008)

Reversible logic synthesis with Fredkin and Peres gates. - James Donald; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2008)

Toward Ideal On-Chip Communication Using Express Virtual Channels. - Amit Kumar 002; Li-Shiuan Peh; Partha Kundu; Niraj K. Jha (IEEE Micro, 2008)

System-Level Dynamic Thermal Management for High-Performance Microprocessors. - Amit Kumar 002; Li Shang; Li-Shiuan Peh; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Analysis and design of a hardware/software trusted platform module for embedded systems. - Najwa Aaraj; Anand Raghunathan; Niraj K. Jha (ACM Trans. Embed. Comput. Syst., 2008)

An energy-aware framework for dynamic software management in mobile computing systems. - Yunsi Fei; Lin Zhong 001; Niraj K. Jha (ACM Trans. Embed. Comput. Syst., 2008)

Automatic Test Generation for Combinational Threshold Logic Networks. - Pallav Gupta; Rui Zhang; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2008)

An architecture for secure software defined radio. - Chunxiao Li 007; Anand Raghunathan; Niraj K. Jha (DATE, 2009)

In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects. - Niket Agarwal; Li-Shiuan Peh; Niraj K. Jha (HPCA, 2009)

Pragmatic design of gated-diode FinFET DRAMs. - Ajay N. Bhoj; Niraj K. Jha (ICCD, 2009)

FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing. - Chun-Yi Lee; Niraj K. Jha (ICCD, 2009)

GARNET: A detailed on-chip network model inside a full-system simulator. - Niket Agarwal; Tushar Krishna; Li-Shiuan Peh; Niraj K. Jha (ISPASS, 2009)

Thermal characterization of BIST, scan design and sequential test methodologies. - Muzaffer O. Simsir; Niraj K. Jha (ITC, 2009)

In-network coherence filtering: snoopy coherence without broadcasts. - Niket Agarwal; Li-Shiuan Peh; Niraj K. Jha (MICRO, 2009)

Low-power FinFET circuit synthesis using multiple supply and threshold voltages. - Prateek Mishra; Anish Muttreja; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2009)

A hybrid nano-CMOS architecture for defect and fault tolerance. - Muzaffer O. Simsir; Srihari Cadambi; Franjo Ivancic; Martin Rötteler; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2009)

A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow. - Wei Zhang 012; Niraj K. Jha; Li Shang (ACM J. Emerg. Technol. Comput. Syst., 2009)

A hybrid nano/CMOS dynamically reconfigurable system - Part I: Architecture. - Wei Zhang 012; Niraj K. Jha; Li Shang (ACM J. Emerg. Technol. Comput. Syst., 2009)

Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture. - Wei Zhang 012; Niraj K. Jha; Li Shang (ACM J. Emerg. Technol. Comput. Syst., 2009)

Editorial Appointments for the 2009-2010 Term. - Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits. - Loganathan Lingappan; Vijay Gangaram; Niraj K. Jha; Sreejit Chakravarty (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A Secure User Interface for Web Applications Running Under an Untrusted Operating System. - Chunxiao Li 007; Anand Raghunathan; Niraj K. Jha (CIT, 2010)

Secure Virtual Machine Execution under an Untrusted Management OS. - Chunxiao Li 007; Anand Raghunathan; Niraj K. Jha (IEEE CLOUD, 2010)

Low-power FinFET circuit synthesis using surface orientation optimization. - Prateek Mishra; Niraj K. Jha (DATE, 2010)

Die-level leakage power analysis of FinFET circuits considering process variations. - Prateek Mishra; Ajay N. Bhoj; Niraj K. Jha (ISQED, 2010)

Fault modeling for FinFET circuits. - Muzaffer O. Simsir; Ajay N. Bhoj; Niraj K. Jha (NANOARCH, 2010)

NanoV: Nanowire-based VLSI design. - Muzaffer O. Simsir; Niraj K. Jha (NANOARCH, 2010)

Gated-diode FinFET DRAMs: Device and circuit design-considerations. - Ajay N. Bhoj; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2010)

FinFET-based power simulator for interconnection networks. - Chun-Yi Lee; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2010)

Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture. - Wei Zhang 012; Niraj K. Jha; Li Shang (ACM J. Emerg. Technol. Comput. Syst., 2010)

Editorial: New Associate Editor Appointments. - Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2010)

CACTI-FinFET: an integrated delay and power modeling framework for FinFET-based caches under process variations. - Chun-Yi Lee; Niraj K. Jha (DAC, 2011)

A low-energy computation platform for data-driven biomedical monitoring algorithms. - Mohammed Shoaib; Niraj K. Jha; Naveen Verma (DAC, 2011)

3D vs. 2D analysis of FinFET logic gates under process variations. - Sourindra Chaudhuri; Niraj K. Jha (ICCD, 2011)

Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology. - Ajay N. Bhoj; Niraj K. Jha (ISQED, 2011)

FinFET-Based Power Management for Improved DPA Resistance with Low Overhead. - Meng Zhang; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2011)

A framework for defending embedded systems against software attacks. - Najwa Aaraj; Anand Raghunathan; Niraj K. Jha (ACM Trans. Embed. Comput. Syst., 2011)

Editorial Announcing a New Editor-in-Chief. - Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A compressed-domain processor for seizure detection to simultaneously reduce computation and communication energy. - Mohammed Shoaib; Niraj K. Jha; Naveen Verma (CICC, 2012)

Enabling advanced inference on sensor nodes through direct use of compressively-sensed signals. - Mohammed Shoaib; Niraj K. Jha; Naveen Verma (DATE, 2012)

Design of Quantum Circuits for Random Walk Algorithms. - Amlan Chakrabarti; Chia-Chun Lin; Niraj K. Jha (ISVLSI, 2012)

Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology. - Sourindra Chaudhuri; Prateek Mishra; Niraj K. Jha (VLSI Design, 2012)

INVISIOS: A Lightweight, Minimally Intrusive Secure Execution Environment. - Divya Arora 001; Najwa Aaraj; Anand Raghunathan; Niraj K. Jha (ACM Trans. Embed. Comput. Syst., 2012)

Secure reconfiguration of software-defined radio. - Chunxiao Li 007; Niraj K. Jha; Anand Raghunathan (ACM Trans. Embed. Comput. Syst., 2012)

A Trusted Virtual Machine in an Untrusted Management Environment. - Chunxiao Li 007; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Serv. Comput., 2012)

SRAM-Based NATURE: A Dynamically Reconfigurable FPGA Based on 10T Low-Power SRAMs. - Ting-Jung Lin; Wei Zhang 012; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Towards trustworthy medical devices and body area networks. - Meng Zhang; Anand Raghunathan; Niraj K. Jha (DAC, 2013)

Localized Heating for Building Energy Efficiency. - Jun Wei Chuah; Chunxiao Li 007; Niraj K. Jha; Anand Raghunathan (VLSI Design, 2013)

Emerging Frontiers in Embedded Security. - Mehran Mozaffari Kermani; Meng Zhang; Anand Raghunathan; Niraj K. Jha (VLSI Design, 2013)

Embedded Reconfigurable Augmented DC-DC Boost Converter for Fast Transient Recovery. - Neeraj Mishra; Niraj K. Jha; Santanu Kapat; Amit Patra (VLSI Design, 2013)

Fin Prin: Analysis and Optimization of FinFET Logic Circuits under PVT Variations. - Yang Yang; Niraj K. Jha (VLSI Design, 2013)

Energy-efficient and Secure Sensor Data Transmission Using Encompression. - Meng Zhang; Mehran Mozaffari Kermani; Anand Raghunathan; Niraj K. Jha (VLSI Design, 2013)

Improving the Trustworthiness of Medical Device Software with Formal Verification Methods. - Chunxiao Li 007; Anand Raghunathan; Niraj K. Jha (IEEE Embed. Syst. Lett., 2013)

Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits. - Aoxiang Tang; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2013)

Design space exploration of FinFET cache. - Aoxiang Tang; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2013)

MedMon: Securing Medical Devices Through Wireless Monitoring and Anomaly Detection. - Meng Zhang; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Biomed. Circuits Syst., 2013)

Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits. - Ajay N. Bhoj; Rajiv V. Joshi; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology. - Ajay N. Bhoj; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2013)

3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits. - Ajay N. Bhoj; Rajiv V. Joshi; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Variable-Pipeline-Stage Router. - Chun-Yi Lee; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Optimized Quantum Gate Library for Various Physical Machine Descriptions. - Chia-Chun Lin; Amlan Chakrabarti; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Algorithm-Driven Architectural Design Space Exploration of Domain-Specific Medical-Sensor Processors. - Mohammed Shoaib; Niraj K. Jha; Naveen Verma (IEEE Trans. Very Large Scale Integr. Syst., 2013)

TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology. - Debajit Bhattacharya; Rajiv V. Joshi; Herschel A. Ainspan; Ninad D. Sathaye; Mohit Bajaj; Suresh Gundapaneni; Niraj K. Jha (CICC, 2014)

FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage. - Sourindra Chaudhuri; Niraj K. Jha (VLSID, 2014)

A defense framework against malware and vulnerability exploits. - Meng Zhang; Anand Raghunathan; Niraj K. Jha (Int. J. Inf. Sec., 2014)

3D vs. 2D Device Simulation of FinFET Logic Gates under PVT Variations. - Sourindra Chaudhuri; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2014)

Accurate Leakage/Delay Estimation for FinFET Standard Cells under PVT Variations using the Response Surface Methodology. - Sourindra M. Chaudhuri; Prateek Mishra; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2014)

Ultra-low-leakage chip multiprocessor design with hybrid FinFET logic styles. - Xianmin Chen; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2014)

QLib: Quantum module library. - Chia-Chun Lin; Amlan Chakrabarti; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2014)

RMDDS: Reed-muller decision diagram synthesis of reversible logic circuits. - Chia-Chun Lin; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2014)

Trustworthiness of Medical Devices and Body Area Networks. - Meng Zhang; Anand Raghunathan; Niraj K. Jha (Proc. IEEE, 2014)

A 0.6-107 µW Energy-Scalable Processor for Directly Analyzing Compressively-Sensed EEG. - Mohammed Shoaib; Kyong-Ho Lee; Niraj K. Jha; Naveen Verma (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs. - Ajay N. Bhoj; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2014)

FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks. - Chun-Yi Lee; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2014)

FTQLS: Fault-Tolerant Quantum Logic Synthesis. - Chia-Chun Lin; Amlan Chakrabarti; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps. - Ting-Jung Lin; Wei Zhang 012; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2014)

FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations. - Yang Yang; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Vibration-based secure side channel for medical devices. - Younghyun Kim 001; Woo Suk Lee; Vijay Raghunathan; Niraj K. Jha; Anand Raghunathan (DAC, 2015)

Synthesis of Quantum Circuits for Dedicated Physical Machine Descriptions. - Philipp Niemann 001; Saikat Basu; Amlan Chakrabarti; Niraj K. Jha; Robert Wille (RC, 2015)

gem5-PVT: A Framework for FinFET System Simulation under PVT Variations. - Xianmin Chen; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2015)

Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare. - Mehran Mozaffari Kermani; Susmita Sur-Kolay; Anand Raghunathan; Niraj K. Jha (IEEE J. Biomed. Health Informatics, 2015)

Energy-Efficient Long-term Continuous Personal Health Monitoring. - Arsalan Mohsen Nia; Mehran Mozaffari Kermani; Susmita Sur-Kolay; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Multi Scale Comput. Syst., 2015)

Design of Efficient Content Addressable Memories in High-Performance FinFET Technology. - Debajit Bhattacharya; Ajay N. Bhoj; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2015)

PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit Synthesis. - Chia-Chun Lin; Susmita Sur-Kolay; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2015)

FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation. - Ting-Jung Lin; Wei Zhang 012; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Signal Processing With Direct Computations on Compressively Sensed Data. - Mohammed Shoaib; Niraj K. Jha; Naveen Verma (IEEE Trans. Very Large Scale Integr. Syst., 2015)

McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations. - Aoxiang Tang; Yang Yang; Chun-Yi Lee; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism. - Sourindra Chaudhuri; Ajay N. Bhoj; Debajit Bhattacharya; Niraj K. Jha (VLSID, 2016)

Ultra-Low-Leakage and High-Performance Logic Circuit Design Using Multiparameter Asymmetric FinFETs. - Sourindra M. Chaudhuri; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2016)

Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs. - Abdullah Guler; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2016)

Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations: Observing the Trends between the 22nm and 14nm Technology Nodes. - Aoxiang Tang; Xun Gao; Lung-Yen Chen; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2016)

Compressed Signal Processing on Nyquist-Sampled Signals. - Jie Lu; Naveen Verma; Niraj K. Jha (IEEE Trans. Computers, 2016)

Ultra-High Density Monolithic 3-D FinFET SRAM With Enhanced Read Stability. - Debajit Bhattacharya; Niraj K. Jha (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Physiological Information Leakage: A New Frontier in Health Information Security. - Arsalan Mohsen Nia; Susmita Sur-Kolay; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Emerg. Top. Comput., 2016)

TCAD-Assisted Capacitance Extraction of FinFET SRAM and Logic Arrays. - Debajit Bhattacharya; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation. - Xianmin Chen; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Reducing Wire and Energy Overheads of the SMART NoC Using a Setup Request Network. - Xianmin Chen; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2016)

GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis. - Aoxiang Tang; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Internet-of-Medical-Things. - Niraj K. Jha (ACM Great Lakes Symposium on VLSI, 2017)

Automated Quantum Circuit Synthesis and Cost Estimation for the Binary Welded Tree Oracle. - Mrityunjay Ghosh; Amlan Chakrabarti; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2017)

CABA: Continuous Authentication Based on BioAura. - Arsalan Mosenia; Susmita Sur-Kolay; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Computers, 2017)

A Comprehensive Study of Security of Internet-of-Things. - Arsalan Mosenia; Niraj K. Jha (IEEE Trans. Emerg. Top. Comput., 2017)

Keep the Stress Away with SoDA: Stress Detection and Alleviation System. - Ayten Ozge Akmandor; Niraj K. Jha (IEEE Trans. Multi Scale Comput. Syst., 2017)

Analytical Modeling of the SMART NoC. - Debajit Bhattacharya; Niraj K. Jha (IEEE Trans. Multi Scale Comput. Syst., 2017)

Wearable Medical Sensor-Based System Design: A Survey. - Arsalan Mosenia; Susmita Sur-Kolay; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Multi Scale Comput. Syst., 2017)

DISASTER: Dedicated Intelligent Security Attacks on Sensor-Triggered Emergency Responses. - Arsalan Mosenia; Susmita Sur-Kolay; Anand Raghunathan; Niraj K. Jha (IEEE Trans. Multi Scale Comput. Syst., 2017)

A Health Decision Support System for Disease Diagnosis Based on Wearable Medical Sensors and Machine Learning Ensembles. - Hongxu Yin; Niraj K. Jha (IEEE Trans. Multi Scale Comput. Syst., 2017)

Improving Convergence and Simulation Time of Quantum Hydrodynamic Simulation: Application to Extraction of Best 10-nm FinFET Parameter Values. - Xiaoliang Dai; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Using a Device State Library to Boost the Performance of TCAD Mixed-Mode Simulation. - Xiaoliang Dai; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Simultaneously ensuring smartness, security, and energy efficiency in Internet-of-Things sensors. - Ayten Ozge Akmandor; Hongxu Yin; Niraj K. Jha (CICC, 2018)

Smart healthcare. - Niraj K. Jha (ICCE, 2018)

Keynotes. - Linus Torvalds; Niraj K. Jha; Gary Davis; Nasir D. Memon; Petronel Bigioi; Swarup Bhunia; Koji Nakao (ICCE, 2018)

Smart Health Care: An Edge-Side Computing Perspective. - Ayten Ozge Akmandor; Niraj K. Jha (IEEE Consumer Electron. Mag., 2018)

Detecting and Alleviating Stress with SoDA. - Ayten Ozge Akmandor; Niraj K. Jha (Computer, 2018)

Smart Healthcare. - Hongxu Yin; Ayten Ozge Akmandor; Arsalan Mosenia; Niraj K. Jha (Found. Trends Electron. Des. Autom., 2018)

Statistical Optimization of FinFET Processor Architectures under PVT Variations Using Dual Device-Type Assignment. - Ye Yu 003; Niraj K. Jha (ACM J. Emerg. Technol. Comput. Syst., 2018)

Genetic Programming for Energy-Efficient and Energy-Scalable Approximate Feature Computation in Embedded Inference Systems. - Jie Lu; Hongyang Jia; Naveen Verma; Niraj K. Jha (IEEE Trans. Computers, 2018)

Smart, Secure, Yet Energy-Efficient, Internet-of-Things Sensors. - Ayten Ozge Akmandor; Hongxu Yin; Niraj K. Jha (IEEE Trans. Multi Scale Comput. Syst., 2018)

PinMe: Tracking a Smartphone User around the World. - Arsalan Mosenia; Xiaoliang Dai; Prateek Mittal; Niraj K. Jha (IEEE Trans. Multi Scale Comput. Syst., 2018)

OpSecure: A Secure Unidirectional Optical Channel for Implantable Medical Devices. - Arsalan Mosenia; Niraj K. Jha (IEEE Trans. Multi Scale Comput. Syst., 2018)

A Hierarchical Inference Model for Internet-of-Things. - Hongxu Yin; Zeyu Wang 004; Niraj K. Jha (IEEE Trans. Multi Scale Comput. Syst., 2018)

A Monolithic 3D Hybrid Architecture for Energy-Efficient Computation. - Ye Yu 003; Niraj K. Jha (IEEE Trans. Multi Scale Comput. Syst., 2018)

Hybrid Monolithic 3-D IC Floorplanner. - Abdullah Guler; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2018)

ChamNet: Towards Efficient Network Design Through Platform-Aware Model Adaptation. - Xiaoliang Dai; Peizhao Zhang; Bichen Wu; Hongxu Yin; Fei Sun; Yanghan Wang; Marat Dukhan; Yunqing Hu; Yiming Wu; Yangqing Jia; Peter Vajda; Matt Uyttendaele; et al. (CVPR, 2019)

Hardware-Guided Symbiotic Training for Compact, Accurate, yet Execution-Efficient LSTM. - Hongxu Yin; Guoyang Chen; Yingmin Li; Shuai Che; Weifeng Zhang 003; Niraj K. Jha (CoRR, 2019)

Software-Defined Design Space Exploration for an Efficient AI Accelerator Architecture. - Ye Yu 003; Yingmin Li; Shuai Che; Niraj K. Jha; Weifeng Zhang 003 (CoRR, 2019)

STEERAGE: Synthesis of Neural Networks Using Architecture Search and Grow-and-Prune Methods. - Shayan Hassantabar; Xiaoliang Dai; Niraj K. Jha (CoRR, 2019)

NeST: A Neural Network Synthesis Tool Based on a Grow-and-Prune Paradigm. - Xiaoliang Dai; Hongxu Yin; Niraj K. Jha (IEEE Trans. Computers, 2019)

Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for Enhanced Read Time and Low Leakage. - Abdullah Guler; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Dreaming to Distill: Data-Free Knowledge Transfer via DeepInversion. - Hongxu Yin; Pavlo Molchanov 001; José M. Álvarez 004; Zhizhong Li 001; Arun Mallya; Derek Hoiem; Niraj K. Jha; Jan Kautz (CVPR, 2020)

INVITED: Efficient Synthesis of Compact Deep Neural Networks. - Wenhan Xia; Hongxu Yin; Niraj K. Jha (DAC, 2020)

Efficient Synthesis of Compact Deep Neural Networks. - Wenhan Xia; Hongxu Yin; Niraj K. Jha (CoRR, 2020)

CovidDeep: SARS-CoV-2/COVID-19 Test Based on Wearable Medical Sensors and Efficient Neural Networks. - Shayan Hassantabar; Novati Stefano; Vishweshwar Ghanakota; Alessandra Ferrari; Gregory N. Nicola; Raffaele Bruno 002; Ignazio R. Marino; Niraj K. Jha (CoRR, 2020)

DISPATCH: Design Space Exploration of Cyber-Physical Systems. - Prerit Terway; Kenza Hamidouche; Niraj K. Jha (CoRR, 2020)

Robot Design With Neural Networks, MILP Solvers and Active Learning. - Sanjai Narain; Emily Mak; Dana Chee; Todd Huster; Jeremy E. J. Cohen; Kishore Pochiraju; Brendan J. Englot; Niraj K. Jha; Karthik S. Narayan (CoRR, 2020)

Grow and Prune Compact, Fast, and Accurate LSTMs. - Xiaoliang Dai; Hongxu Yin; Niraj K. Jha (IEEE Trans. Computers, 2020)

McPAT-Monolithic: An Area/Power/Timing Architecture Modeling Framework for 3-D Hybrid Monolithic Multicore Systems. - Abdullah Guler; Niraj K. Jha (IEEE Trans. Very Large Scale Integr. Syst., 2020)

MHDeep: Mental Health Disorder Detection System based on Body-Area and Deep Neural Networks. - Shayan Hassantabar; Joe Zhang; Hongxu Yin; Niraj K. Jha (CoRR, 2021)

HW/SW Framework for Improving the Safety of Implantable and Wearable Medical Devices. - Malin Prematilake; Younghyun Kim 001; Vijay Raghunathan; Anand Raghunathan; Niraj K. Jha (CoRR, 2021)

SECRET: Semantically Enhanced Classification of Real-World Tasks. - Ayten Ozge Akmandor; Jorge Ortiz 001; Irene Manotas; Bongjun Ko; Niraj K. Jha (IEEE Trans. Computers, 2021)

Software-Defined Design Space Exploration for an Efficient DNN Accelerator Architecture. - Ye Yu 003; Yingmin Li; Shuai Che; Niraj K. Jha; Weifeng Zhang 003 (IEEE Trans. Computers, 2021)

CovidDeep: SARS-CoV-2/COVID-19 Test Based on Wearable Medical Sensors and Efficient Neural Networks. - Shayan Hassantabar; Novati Stefano; Vishweshwar Ghanakota; Alessandra Ferrari; Gregory N. Nicola; Raffaele Bruno 002; Ignazio R. Marino; Kenza Hamidouche; Niraj K. Jha (IEEE Trans. Consumer Electron., 2021)

DiabDeep: Pervasive Diabetes Diagnosis Based on Wearable Medical Sensors and Efficient Neural Networks. - Hongxu Yin; Bilal Mukadam; Xiaoliang Dai; Niraj K. Jha (IEEE Trans. Emerg. Top. Comput., 2021)

YSUY: Your Smartphone Understands You - Using Machine Learning to Address Fundamental Human Needs. - Ayten Ozge Akmandor; Xiaoliang Dai; Niraj K. Jha (IEEE Trans. Syst. Man Cybern. Syst., 2021)

ML-FEED: Machine Learning Framework for Efficient Exploit Detection. - Tanujay Saha; Tamjid Al Rahat; Najwa Aaraj; Yuan Tian 001; Niraj K. Jha (TPS-ISA, 2022)

CURIOUS: Efficient Neural Architecture Search Based on a Performance Predictor and Evolutionary Search. - Shayan Hassantabar; Xiaoliang Dai; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

SCANN: Synthesis of Compact and Accurate Neural Networks. - Shayan Hassantabar; Zeyu Wang 004; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Fast Design Space Exploration of Nonlinear Systems: Part I. - Sanjai Narain; Emily Mak; Dana Chee; Brendan J. Englot; Kishore Pochiraju; Niraj K. Jha; Karthik S. Narayan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Fast Design Space Exploration of Nonlinear Systems: Part II. - Prerit Terway; Kenza Hamidouche; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

GRAVITAS: Graphical Reticulated Attack Vectors for Internet-of-Things Aggregate Security. - Jacob Brown; Tanujay Saha; Niraj K. Jha (IEEE Trans. Emerg. Top. Comput., 2022)

Incremental Learning Using a Grow-and-Prune Paradigm With Efficient Neural Networks. - Xiaoliang Dai; Hongxu Yin; Niraj K. Jha (IEEE Trans. Emerg. Top. Comput., 2022)

Convolutional Autoencoder-Based Transfer Learning for Multi-Task Image Inferences. - Jie Lu; Naveen Verma; Niraj K. Jha (IEEE Trans. Emerg. Top. Comput., 2022)

SHARKS: Smart Hacking Approaches for RisK Scanning in Internet-of-Things and Cyber-Physical Systems Based on Machine Learning. - Tanujay Saha; Najwa Aaraj; Neel Ajjarapu; Niraj K. Jha (IEEE Trans. Emerg. Top. Comput., 2022)

Machine Learning Assisted Security Analysis of 5G-Network-Connected Systems. - Tanujay Saha; Najwa Aaraj; Niraj K. Jha (IEEE Trans. Emerg. Top. Comput., 2022)

Fully Dynamic Inference With Deep Neural Networks. - Wenhan Xia; Hongxu Yin; Xiaoliang Dai; Niraj K. Jha (IEEE Trans. Emerg. Top. Comput., 2022)

Towards Execution-Efficient LSTMs via Hardware-Guided Grow-and-Prune Paradigm. - Hongxu Yin; Guoyang Chen; Yingmin Li; Shuai Che; Weifeng Zhang 003; Niraj K. Jha (IEEE Trans. Emerg. Top. Comput., 2022)

SPRING: A Sparsity-Aware Reduced-Precision Monolithic 3D CNN Accelerator Architecture for Training and Inference. - Ye Yu 003; Niraj K. Jha (IEEE Trans. Emerg. Top. Comput., 2022)

MHDeep: Mental Health Disorder Detection System Based on Wearable Sensors and Artificial Neural Networks. - Shayan Hassantabar; Joe Zhang; Hongxu Yin; Niraj K. Jha (ACM Trans. Embed. Comput. Syst., 2022)

AIMED: AI-Mediated Exploration of Design: An Experience Report. - Sanjai Narain; Dana Chee; Pranav Iyer; Emily Mak; Ricardo Valdez; Manli Zhu; Niraj K. Jha; Jaime F. Fisac; Kai-Chieh Hsu; Prerit Terway; Kishore Pochiraju; Brendan J. Englot; et al. (CPS-IoT Week Workshops, 2023)

Im-Promptu: In-Context Composition from Image Prompts. - Bhishma Dedhia; Michael Chang 003; Jake Snell; Tom Griffiths 001; Niraj K. Jha (NeurIPS, 2023)

ML-FEED: Machine Learning Framework for Efficient Exploit Detection (Extended version). - Tanujay Saha; Tamjid Al Rahat; Najwa Aaraj; Yuan Tian 001; Niraj K. Jha (CoRR, 2023)

EdgeTran: Co-designing Transformers for Efficient Inference on Mobile Edge Platforms. - Shikhar Tuli; Niraj K. Jha (CoRR, 2023)

SECRETS: Subject-Efficient Clinical Randomized Controlled Trials using Synthetic Intervention. - Sayeri Lala; Niraj K. Jha (CoRR, 2023)

BREATHE: Second-Order Gradients and Heteroscedastic Emulation based Design Space Exploration. - Shikhar Tuli; Niraj K. Jha (CoRR, 2023)

FlexiBERT: Are Current Transformer Architectures too Homogeneous and Rigid? - Shikhar Tuli; Bhishma Dedhia; Shreshth Tuli; Niraj K. Jha (J. Artif. Intell. Res., 2023)

CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework. - Shikhar Tuli; Chia-Hao Li; Ritvik Sharma; Niraj K. Jha (ACM Trans. Embed. Comput. Syst., 2023)

TUTOR: Training Neural Networks Using Decision Rules as Model Priors. - Shayan Hassantabar; Prerit Terway; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

INFORM: Inverse Design Methodology for Constrained Multiobjective Optimization. - Prerit Terway; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

REPAIRS: Gaussian Mixture Model-based Completion and Optimization of Partially Specified Systems. - Prerit Terway; Niraj K. Jha (ACM Trans. Embed. Comput. Syst., 2023)

SCouT: Synthetic Counterfactuals via Spatiotemporal Transformers for Actionable Healthcare. - Bhishma Dedhia; Roshini Balasubramanian; Niraj K. Jha (ACM Trans. Comput. Heal., 2023)

AccelTran: A Sparsity-Aware Accelerator for Dynamic Inference With Transformers. - Shikhar Tuli; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

TransCODE: Co-Design of Transformers and Accelerators for Efficient Training and Inference. - Shikhar Tuli; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Zero-TPrune: Zero-Shot Token Pruning Through Leveraging of the Attention Graph in Pre-Trained Transformers. - Hongjie Wang 002; Bhishma Dedhia; Niraj K. Jha (CVPR, 2024)

Attention-Driven Training-Free Efficiency Enhancement of Diffusion Models. - Hongjie Wang 002; Difan Liu; Yan Kang; Yijun Li; Zhe Lin; Niraj K. Jha; Yuchen Liu (CVPR, 2024)

DynaMo: Accelerating Language Model Inference with Dynamic Multi-Token Sampling. - Shikhar Tuli; Chi-Heng Lin; Yen-Chang Hsu; Niraj K. Jha; Yilin Shen; Hongxia Jin (NAACL-HLT, 2024)

PAGE: Domain-Incremental Adaptation with Past-Agnostic Generative Replay for Smart Healthcare. - Chia-Hao Li; Niraj K. Jha (CoRR, 2024)

CONFINE: Conformal Prediction for Interpretable Neural Networks. - Linhui Huang; Sayeri Lala; Niraj K. Jha (CoRR, 2024)

METRIK: Measurement-Efficient Randomized Controlled Trials using Transformers with Input Masking. - Sayeri Lala; Niraj K. Jha (CoRR, 2024)

Learning Interpretable Differentiable Logic Networks. - Chang Yue; Niraj K. Jha (CoRR, 2024)

COMFORT: A Continual Fine-Tuning Framework for Foundation Models Targeted at Consumer Healthcare. - Chia-Hao Li; Niraj K. Jha (CoRR, 2024)

EdgeTran: Device-Aware Co-Search of Transformers for Efficient Inference on Mobile Edge Platforms. - Shikhar Tuli; Niraj K. Jha (IEEE Trans. Mob. Comput., 2024)

CTRL: Clustering Training Losses for Label Error Detection. - Chang Yue; Niraj K. Jha (IEEE Trans. Artif. Intell., 2024)

DOCTOR: A Multi-Disease Detection Continual Learning Framework Based on Wearable Medical Sensors. - Chia-Hao Li; Niraj K. Jha (ACM Trans. Embed. Comput. Syst., 2024)

LinGen: Towards High-Resolution Minute-Length Text-to-Video Generation with Linear Computational Complexity. - Hongjie Wang 002; Chih-Yao Ma; Yen-Cheng Liu; Ji Hou; Tao Xu; Jialiang Wang 001; Felix Juefei-Xu; Yaqiao Luo; Peizhao Zhang; Tingbo Hou; Peter Vajda; Niraj K. Jha; et al. (CVPR, 2025)

Neural Slot Interpreters: Grounding Object Semantics in Emergent Slot Representations. - Bhishma Dedhia; Niraj K. Jha (Trans. Mach. Learn. Res., 2025)

Generating, Fast and Slow: Scalable Parallel Video Generation with Video Interface Networks. - Bhishma Dedhia; David Bourgin; Krishna Kumar Singh; Yuheng Li; Yan Kang; Zhan Xu; Niraj K. Jha; Yuchen Liu (CoRR, 2025)

Learning Interpretable Differentiable Logic Networks for Tabular Regression. - Chang Yue; Niraj K. Jha (CoRR, 2025)

Bottom-up Domain-specific Superintelligence: A Reliable Knowledge Graph is What We Need. - Bhishma Dedhia; Yuval Kansal; Niraj K. Jha (CoRR, 2025)