FPGA-Based Acceleration of LU decomposition for Analog and RF Circuit Simulation. - Yogesh Mahajan; Shashank Obla; Mini K. Namboothiripad; Mandar J. Datar; Niraj N. Sharma; Sachin B. Patkar (VLSID, 2020)

CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism. - Riya Jain; Niraj N. Sharma; Farhad Merchant; Sachin B. Patkar; Rainer Leupers (CoRR, 2020)

CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism. - Niraj N. Sharma; Riya Jain; Mohana Madhumita Pokkuluri; Sachin B. Patkar; Rainer Leupers; Rishiyur S. Nikhil; Farhad Merchant (J. Syst. Archit., 2023)