A Novel Approach to Cell Formation. - Radim Belohlávek; Niranjan Kulkarni; Vilém Vychodil (ICFCA, 2009)

Identification of Threshold Functions and Synthesis of Threshold Networks. - Tejaswi Gowda; Sarma B. K. Vrudhula; Niranjan Kulkarni; Krzysztof S. Berezowski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Minimizing area and power of sequential CMOS circuits using threshold decomposition. - Niranjan Kulkarni; Nishant Nukala; Sarma B. K. Vrudhula (ICCAD, 2012)

A fast, energy efficient, field programmable threshold-logic array. - Niranjan Kulkarni; Jinghua Yang; Sarma B. K. Vrudhula (FPT, 2014)

Integration of threshold logic gates with RRAM devices for energy efficient and robust operation. - Jinghua Yang; Niranjan Kulkarni; Shimeng Yu; Sarma B. K. Vrudhula (NANOARCH, 2014)

Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture. - Nishant Nukala; Niranjan Kulkarni; Sarma B. K. Vrudhula (J. Parallel Distributed Comput., 2014)

Dynamic and leakage power reduction of ASICs using configurable threshold logic gates. - Jinghua Yang; Joseph Davis; Niranjan Kulkarni; Jae-sun Seo; Sarma B. K. Vrudhula (CICC, 2015)

Design of threshold logic gates using emerging devices. - Sarma B. K. Vrudhula; Niranjan Kulkarni; Jinghua Yang (ISCAS, 2015)

Fast and robust differential flipflops and their extension to multi-input threshold gates. - Jinghua Yang; Niranjan Kulkarni; Joseph Davis; Sarma B. K. Vrudhula (ISCAS, 2015)

Digital IP protection using threshold voltage control. - Joseph Davis; Niranjan Kulkarni; Jinghua Yang; Aykut Dengi; Sarma B. K. Vrudhula (ISQED, 2016)

Efficient Enumeration of Unidirectional Cuts for Technology Mapping of Boolean Networks. - Niranjan Kulkarni; Sarma B. K. Vrudhula (CoRR, 2016)

An Enhanced Edge Adaptive Steganography Approach Using Threshold Value for Region Selection. - Sachin Mungmode; R. R. Sedamkar; Niranjan Kulkarni (CoRR, 2016)

Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops. - Niranjan Kulkarni; Jinghua Yang; Jae-sun Seo; Sarma B. K. Vrudhula (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits. - Niranjan Kulkarni; Aykut Dengi; Sarma B. K. Vrudhula (DAC, 2017)

A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking. - Ankit Wagle; Jinghua Yang; Niranjan Kulkarni; Sarma B. K. Vrudhula (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)