Low Voltage, Low Power Folding Amplifier for Folding & Interpolating ADC. - Shruti Oza; N. M. Devashrayee (ARTCom, 2009)

Survey of Test Data Compression Technique Emphasizing Code Based Schemes. - Usha Sandeep Mehta; Kankar S. Dasgupta; Nirnjan M. Devashrayee (DSD, 2009)

Combining unspecified test data bit filling methods and run length based codes to estimate compression, power and area overhead. - Usha Sandeep Mehta; Kankar S. Dasgupta; Niranjan M. Devashrayee (APCCAS, 2010)

Low voltage, high folding rate folding amplifier. - Shruti Oza; N. M. Devashrayee (ICWET, 2010)

Hamming Distance Based 2-D Reordering with Power Efficient Don't Care Bit Filling: Optimizing the test data compression method. - Usha Sandeep Mehta; Niranjan M. Devashrayee; Kankar S. Dasgupta (SoC, 2010)

Hamming Distance Based Reordering and Columnwise Bit Stuffing with Difference Vector: A Better Scheme for Test Data Compression with Run Length Based Codes. - Usha Sandeep Mehta; Kankar S. Dasgupta; Nirnjan M. Devashrayee (VLSI Design, 2010)

Modified Selective Huffman Coding for Optimization of Test Data Compression, Test Application Time and Area Overhead. - Usha Sandeep Mehta; Kankar S. Dasgupta; Nirnjan M. Devashrayee (J. Electron. Test., 2010)

Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds? - A Survey. - Usha Sandeep Mehta; Kankar S. Dasgupta; Niranjan M. Devashrayee (VLSI Design, 2010)

A novel OTA and FVF based second generation current conveyor. - A. P. Naik; N. M. Devashrayee (ICWET, 2011)

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey. - Usha Sandeep Mehta; Kankar S. Dasgupta; Niranjan M. Devashrayee (VLSI Design, 2011)

Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method. - Usha Sandeep Mehta; Kankar S. Dasgupta; Nirnjan M. Devashrayee (VLSI Design, 2011)

Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology. - Vijay Savani; N. M. Devashrayee (VDAT, 2015)

Development of Radiation Hardened by Design(RHBD) primitive gates using 0.18μm CMOS technology. - Rakesh Trivedi; N. M. Devashrayee; Usha Sandeep Mehta; N. M. Desai; Himanshu Patel (VDAT, 2015)

Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator. - Vijay Savani; N. M. Devashrayee (Microelectron. J., 2018)