Hardware efficient recursive VLSI architecture for multilevel lifting 2-D DWT. - Anand D. Darji; Nisarg Trivedi; S. N. Merchant; Arun N. Chandorkar (ISCAS, 2012)

Truncated Matrix Completion - An Empirical Study. - Rishhabh Naik; Nisarg Trivedi; Davoud Ataee Tarzanagh; Laura Balzano (EUSIPCO, 2022)

Modelling & Steady State Compliance Testing of an Improved Time Synchronized Phasor Measurement Unit Based on IEEE Standard C37.118.1. - Nisarg Trivedi (CoRR, 2025)