Microarchitecture of HaL's CPU. - Niteen Patkar; Akira Katsuno; Simon Li; Tak Maruyama; Sunil Savkar; Mike Simone; Gene Shen; Ravi Swami; DeForest Tovey (COMPCON, 1995)

Error Detection and Handling in a Superscalar, Speculative Out-of-Order Execution Processor System. - Nirmal R. Saxena; Chien Chen; Ravi Swami; Hideki Osone; Shalesh Thusoo; David Lyon; David Chang; Anand Dharmaraj; Niteen Patkar; Yizhi Lu; Ben Chia (FTCS, 1995)

Implementation Trade-Offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor. - Mike Simone; A. Essen; A. Ike; A. Krishnamoorthy; Tak Maruyama; Niteen Patkar; M. Ramaswami; Michael Shebanow; V. Thirumalaiswamy; DeForest Tovey (ISCA, 1995)

SPARC64: a 64-b 64-active-instruction out-of-order-execution MCM processor. - Ted Williams; Niteen Patkar; Gene Shen (IEEE J. Solid State Circuits, 1995)

Testing of Vega2, a chip multi-processor with spare processors. - Samy Makar; Tony Altinis; Niteen Patkar; Janet Wu (ITC, 2007)