On the design of band-pass quadrature ΣΔ modulators. - Kumar Y. B. Nithin; Selçuk Talay; Franco Maloberti (APCCAS, 2008)

Complex Cascaded Bandpass SigmaDelta ADC Design. - Kumar Y. B. Nithin; Selçuk Talay; Franco Maloberti (ISCAS, 2009)

Slew-rate and Gain Enhancement in Two Stage Operational Amplifiers. - Aldo Pena-Perez; Kumar Y. B. Nithin; Edoardo Bonizzoni; Franco Maloberti (ISCAS, 2009)

Interference rejection in delay line based quadrature band-pass ΣΔ modulators. - Kumar Y. B. Nithin; Edoardo Bonizzoni; Amit Patra; Franco Maloberti (ISCAS, 2012)

A 1.96-mW, 2.6-MHz bandwidth discrete time quadrature band-pass ΣΔ modulator. - Kumar Y. B. Nithin; Hervé Caracciolo; Edoardo Bonizzoni; A. Parra; Franco Maloberti (ISCAS, 2013)

Two-Path Quadrature Cascaded Band-Pass Sigma-Delta Modulators. - Kumar Y. B. Nithin; Edoardo Bonizzoni; Amit Patra; Franco Maloberti (VLSI Design, 2013)

Low power, high speed error tolerant multiplier using approximate adders. - Karri Manikantta Reddy; Kumar Y. B. Nithin; Dheeraj Sharma; M. H. Vasantha (VDAT, 2015)

FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images. - Pranose J. Edavoor; Sithara Raveendran; Arjun T. V.; Sumesh K. P.; Kumar Y. B. Nithin; M. H. Vasantha (ICCCNT, 2016)

Design and Implementation of Tunable Bandpass Filter for Biomedical Applications. - Saurabh B. Kaurati; Nithin Y. B. Kumar; Shivnarayan Patidar; M. H. Vasantha (iNIS, 2016)

Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor. - S. Ahish; Dheeraj Sharma; M. H. Vasantha; Kumar Y. B. Nithin (ISVLSI, 2016)

Design of Low Power 5-Bit Hybrid Flash ADC. - S. M. Mayur; Siddharth R. K.; Kumar Y. B. Nithin; M. H. Vasantha (ISVLSI, 2016)

A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core. - B. Naresh Kumar Reddy; M. H. Vasantha; Kumar Y. B. Nithin (ISVLSI, 2016)

Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell. - A. Venkatareddy; Sithara Raveendran; Kumar Y. B. Nithin; M. H. Vasantha (VLSID, 2016)

High Performance Sense Amplifier Based Flip Flop for Driver Applications. - Anoop D; Nithin Kumar Yernad Balachandra; Vasantha Moodabettu Harishchandra (iNIS, 2017)

Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing. - Sumit Khalapure; Siddharth R. K.; Kumar Y. B. Nithin; M. H. Vasantha (ISVLSI, 2017)

Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC. - S. M. Mayur; Siddharth R. K.; Kumar Y. B. Nithin; M. H. Vasantha (ISVLSI, 2017)

A 0.5 V Low Power OTA-C Low Pass Filter for ECG Detection. - Rakhi R.; Abhijeet D. Taralkar; M. H. Vasantha; Kumar Y. B. Nithin (ISVLSI, 2017)

System level fault-tolerance core mapping and FPGA-based verification of NoC. - Naresh Kumar Reddy Becchu; Vasantha Moodabettu Harishchandra; Nithin Kumar Yernad Balachandra (Microelectron. J., 2017)

High-performance and energy-efficient fault-tolerance core mapping in NoC. - Naresh Kumar Reddy Beechu; Vasantha Moodabettu Harishchandra; Nithin Kumar Yernad Balachandra (Sustain. Comput. Informatics Syst., 2017)

A 0.5 V Low Power DTMOS OTA-C Filter for ECG Sensing Applications. - Purnima Kalekar; Prasad Vernekar; M. H. Vasantha; Y. B. Nithin Kumar; Edoardo Bonizzoni (IEEE SENSORS, 2018)

A Low-Power Auxiliary Circuit for Level-Crossing ADCs in IoT-Sensor Applications. - Siddharth R. K.; Kumar Y. B. Nithin; M. H. Vasantha; Edoardo Bonizzoni (ISCAS, 2018)

FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics. - Sampada Barve; Sithara Raveendran; Charudatta Korde; Trilochan Panigrahi; Nithin Y. B. Kumar; M. H. Vasantha (iSES, 2018)

Design of Area-Power-Delay Efficient Square Root Carry Select Adder. - Chetan Kamble; Siddharth R. K.; Shivnarayan Patidar; M. H. Vasantha; Nithin Y. B. Kumar (iSES, 2018)

Design and Analysis of Approximate Multipliers for Error-Tolerant Applications. - Anirudha Pandey; Karri Manikantta Reddy; Praveen Yadav; Nithin Y. B. Kumar; M. H. Vasantha (iSES, 2018)

Performance Enhancement of Split Length Compensated Operational Amplifiers. - Donel Anto; Abhijeet D. Taralkar; Kumar Y. B. Nithin; M. H. Vasantha (ISVLSI, 2018)

An Asynchronous Analog to Digital Converter for Surveillance Camera Applications. - Siddharth R. K.; Sunil R.; Nithin Y. B. Kumar; M. H. Vasantha; Edoardo Bonizzoni (ISVLSI, 2018)

Design of Approximate Dividers for Error Tolerant Applications. - Karri Manikantta Reddy; M. H. Vasantha; Kumar Y. B. Nithin; Devesh Dwivedi (MWSCAS, 2018)

Low Power Approximate Multipliers With Truncated Carry Propagation for LSBs. - Praveen Yadav; Anirudha Pandey; Karri Manikantta Reddy; K. J. Ravi Prasad; M. H. Vasantha; Nithin Y. B. Kumar (MWSCAS, 2018)

Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter. - Sithara Raveendran; Pranose J. Edavoor; Nithin Y. B. Kumar; M. H. Vasantha (TENCON, 2018)

Characterization of a Novel Low Leakage Power-Efficient Asymmetric 7T SRAM Cell. - Dhavala Shashidhar; Vivek Sharma 002; Gurusiddappa R. Prashanth; Nithin Y. B. Kumar; M. H. Vasantha (TENCON, 2018)

A Novel Low Power G m-C Continuous-Time Analog Filter with Wide Tuning Range. - P. S. Veerendranath; M. H. Vasantha; Kumar Y. B. Nithin; Edoardo Bonizzoni (VLSID, 2018)

An energy-efficient fault-aware core mapping in mesh-based network on chip systems. - Naresh Kumar Reddy Beechu; Vasantha Moodabettu Harishchandra; Nithin Kumar Yernad Balachandra (J. Netw. Comput. Appl., 2018)

Hardware implementation of fault tolerance NoC core mapping. - Naresh Kumar Reddy Beechu; Vasantha Moodabettu Harishchandra; Nithin Kumar Yernad Balachandra (Telecommun. Syst., 2018)

Energy-Aware and Reliability-Aware Mapping for NoC-Based Architectures. - Naresh Kumar Reddy Beechu; Vasantha Moodabettu Harishchandra; Nithin Kumar Yernad Balachandra (Wirel. Pers. Commun., 2018)

Two-Step Flash ADC Using Standard Cell Based Flash ADCs. - Rahul E.; Siddharth R. K.; Vivek Sharma 002; M. H. Vasantha; Nithin Kumar Yernad Balachandra (iSES, 2019)

Process Corner Calibration for Standard Cell Based Flash ADC. - Pradeep R.; Siddharth R. K.; Nithin Kumar Yernad Balachandra; Vasantha Moodabettu Harishchandra (iSES, 2019)

An Asynchronous Analog to Digital Converter for Video Camera Applications. - Sunil R.; Siddharth R. K.; Nithin Y. B. Kumar; M. H. Vasantha (ISVLSI, 2019)

Self Timed SRAM Array with Enhanced low Voltage Read and Write Capability. - Prasad Vernekar; Nithin Kumar Yernad Balachandra; Vasantha Moodabettu Harishchandra (ISVLSI, 2019)

Design and Analysis of Energy Efficient Reversible Logic based Full Adder. - Jagadeesh Pujar; Sithara Raveendran; Trilochan Panigrahi; Vasantha M. H.; Nithin Kumar Y. B. (MWSCAS, 2019)

Current Conveyor based Novel Gyrator filter for Biomedical Sensor Applications. - P. S. Veerendranath; Vivek Sharma 002; Nithin Y. B. Kumar; M. H. Vasantha; Edoardo Bonizzoni (TENCON, 2019)

A 1 V, 39 μ W, 5-bit Multi-Level Comparator based Flash ADC. - Nitish Kumar; Siddharth R. K.; Nithin Y. B. Kumar; M. H. Vasantha (iSES, 2020)

A 1.8 V Quadrature Phase LC Oscillator for 5G Applications. - Sanmitra Bharat Naik; Siddharth R. K.; Anirban Chatterjee; Nithin Kumar Y. B.; M. H. Vasantha; Ramnath Kini (iSES, 2020)

A 1.8 V, Mode-Configurable Hybrid Smart ADC. - Tejas J. Shahane; Siddharth R. K.; Kumar Y. B. Nithin; Vasantha M. H. (iSES, 2020)

A Novel Single Event Upset Tolerant 12T Memory Cell for Aerospace Applications. - Suraj Dohar; Siddharth R. K.; Vasantha M. H.; Nithin Kumar Y. B. (ISVLSI, 2020)

A Wideband 12 Phase Ring Oscillator for 5G Applications. - Sanmitra Bharat Naik; Siddharth R. K.; Anirban Chatterjee; Nithin Kumar Y. B.; Vasantha M. H.; Ramnath Kini (MWSCAS, 2020)

Reversible Logic Implementation of Image Denoising for Grayscale Images. - Sithara Raveendran; Pranose J. Edavoor; Nithin Kumar Y. B.; M. H. Vasantha (MWSCAS, 2020)

An Approximate Low-Power Lifting Scheme Using Reversible Logic. - Sithara Raveendran; Pranose J. Edavoor; Nithin Y. B. Kumar; M. H. Vasantha (IEEE Access, 2020)

6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process. - Siddharth Rajkumar Kala; Sushma Chandaka; Nithin Kumar Yernad Balachandra; Vasantha Moodabettu Harishchandra; Edoardo Bonizzoni (IET Circuits Devices Syst., 2020)

IET Circuits, Devices & Systems. - Vivek Sharma 002; Nithin Kumar Y. B.; Vasantha M. H. (IET Circuits Devices Syst., 2020)

Design and implementation of image kernels using reversible logic gates. - Sithara Raveendran; Pranose J. Edavoor; Nithin Kumar Yernad Balachandra; Vasantha Moodabettu Harishchandra (IET Image Process., 2020)

Approximate radix-8 Booth multiplier for low power and high speed applications. - Bipul Boro; Karri Manikantta Reddy; Nithin Y. B. Kumar; M. H. Vasantha (Microelectron. J., 2020)

Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications. - Siddharth R. K.; Nithin Y. B. Kumar; M. H. Vasantha (SN Comput. Sci., 2020)

A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications. - Siddharth R. K.; Y. Jaya Satyanarayana; Nithin Y. B. Kumar; M. H. Vasantha; Edoardo Bonizzoni (IEEE Trans. Circuits Syst., 2020)

Design of Approximate Booth Squarer for Error-Tolerant Computing. - Karri Manikantta Reddy; M. H. Vasantha; Nithin Y. B. Kumar; Devesh Dwivedi (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 1-V, 5-Bit, 180-µW, Differential Pulse Position Modulation ADC in 65-nm CMOS Process. - Peta Guruprakashkumar; Siddharth R. K.; Nithin Kumar Y. B.; Vasantha M. H.; Edoardo Bonizzoni (ISCAS, 2021)

Training of Generative Adversarial Networks using Particle Swarm Optimization Algorithm. - K. G. Shreeharsha; Charudatta Korde; M. H. Vasantha; Y. B. Nithin Kumar (iSES, 2021)

A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented DAC for Video Applications. - Shiv Chandra Kumar; Siddharth R. K.; Nithin Kumar Y. B.; M. H. Vasantha (ISVLSI, 2021)

A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications. - Sanmitra Bharat Naik; Siddharth R. K.; Anirban Chatterjee; Kumar Y. B. Nithin; M. H. Vasantha; Ramnath Kini (VLSID, 2021)

Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic. - Sithara Raveendran; Pranose J. Edavoor; Nithin Kumar Yernad Balachandra; M. H. Vasantha (IEEE Access, 2021)

$ pm , 0.5$ V, 254 $ upmu $W Second-Order Tunable Biquad Low-Pass Filter with 7.3 fJ FOM Using a Novel Low-Voltage Fully Balanced Current-Mode Circuit. - P. S. Veerendranath; Vivek Sharma 002; M. H. Vasantha; Y. B. Nithin Kumar (Circuits Syst. Signal Process., 2021)

Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications. - Karri Manikantta Reddy; M. H. Vasantha; Nithin Y. B. Kumar; Ch. Keshava Gopal; Devesh Dwivedi (Integr., 2021)

A Novel Complex Filter Design With Dual Feedback for High Frequency Wireless Receiver Applications. - P. S. Veerendranath; Vivek Sharma 002; M. H. Vasantha; Y. B. Nithin Kumar (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic. - Sithara Raveendran; Pranose J. Edavoor; Y. B. Nithin Kumar; M. H. Vasantha (ISCAS, 2022)

A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS. - R. D. Balaji; Siddharth R. K.; Sanmitra Bharat Naik; Y. B. Nithin Kumar; M. H. Vasantha; Edoardo Bonizzoni (ISCAS, 2023)

Approximate Three-Operand Binary Adder for Error-Resilient Applications. - Darshan Halliyavar; Siddharth R. K.; Vasantha M. H.; Nithin Kumar Y. B.; Sithara Raveendran (iSES, 2023)

A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process. - Rupesh D. Kadhao; Siddharth R. K.; Nithin Kumar Y. B.; Vasantha M. H.; Devesh Dwivedi (VLSID, 2023)

Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing. - K. G. Shreeharsha; Siddharth R. K.; M. H. Vasantha; Y. B. Nithin Kumar (IEEE Access, 2023)

N-Parallel Paths-Based D-Latch for High-Speed Applications. - Rakhi R.; Siddharth R. K.; K. G. Shreeharsha; M. H. Vasantha; Nithin Kumar Yernad Balachandra (IEEE Access, 2024)

An Error Bound Particle Swarm Optimization for Analog Circuit Sizing. - K. G. Shreeharsha; Siddharth R. K.; M. H. Vasantha; Kumar Y. B. Nithin (IEEE Access, 2024)