Towards provably-secure analog and mixed-signal locking against overproduction. - Nithyashankari Gummidipoondi Jayasankaran; Adriana C. Sanabria-Borbon; Edgar Sánchez-Sinencio; Jiang Hu 001; Jeyavijayan Rajendran (ICCAD, 2018)

Breaking Analog Locking Techniques via Satisfiability Modulo Theories. - Nithyashankari Gummidipoondi Jayasankaran; Adriana C. Sanabria-Borbon; Amr Abuellil; Edgar Sánchez-Sinencio; Jiang Hu 001; Jeyavijayan Rajendran (ITC, 2019)

Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits. - Adriana C. Sanabria-Borbon; Nithyashankari Gummidipoondi Jayasankaran; Sir Yee Lee; Edgar Sánchez-Sinencio; Jiang Hu 001; Jeyavijayan (JV) Rajendran (ITC, 2020)

Keynote: A Disquisition on Logic Locking. - Abhishek Chakraborty 001; Nithyashankari Gummidipoondi Jayasankaran; Yuntao Liu 001; Jeyavijayan Rajendran; Ozgur Sinanoglu; Ankur Srivastava 001; Yang Xie 001; Muhammad Yasin; Michael Zuzak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Breaking Analog Locking Techniques. - Nithyashankari Gummidipoondi Jayasankaran; Adriana C. Sanabria-Borbon; Amr Abuellil; Edgar Sánchez-Sinencio; Jiang Hu 001; Jeyavijayan Rajendran (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Analog/RF IP Protection: Attack Models, Defense Techniques, and Challenges. - Adriana C. Sanabria-Borbon; Nithyashankari Gummidipoondi Jayasankaran; Jiang Hu 001; Jeyavijayan Rajendran; Edgar Sánchez-Sinencio (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Securing Cloud FPGAs Against Power Side-Channel Attacks: A Case Study on Iterative AES. - Nithyashankari Gummidipoondi Jayasankaran; Hao Guo; Satwik Patnaik; Jeyavijayan Rajendran; Jiang Hu 001 (CoRR, 2023)