5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS. - Sriram R. Vangal; Mark A. Anders 001; Nitin Borkar; Erik Seligman; Venkatesh Govindarajulu; Vasantha Erraguntla; Howard Wilson; Amaresh Pangal; Venkat Veeramachaneni; James W. Tschanz; Yibin Ye; Dinesh Somasekhar; et al. (IEEE J. Solid State Circuits, 2002)

A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS. - Yatin Vasant Hoskote; Bradley A. Bloechel; Gregory E. Dermer; Vasantha Erraguntla; David Finan; Jason Howard; Dan Klowden; Siva G. Narendra; Greg Ruhl; James W. Tschanz; Sriram R. Vangal; Venkat Veeramachaneni; et al. (IEEE J. Solid State Circuits, 2003)

Design Challenges in Sub-100nm High Performance Microprocessors. - Siva G. Narendra; Vasantha Erraguntla; James W. Tschanz; Nitin Borkar (VLSI Design, 2004)

A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS. - Muhammad M. Khellah; Nam-Sung Kim; Jason Howard; Gregory Ruhl; Yibin Ye; James W. Tschanz; Dinesh Somasekhar; Nitin Borkar; Fatih Hamzaoglu; Gunjan Pandya; Ali Farhang; Kevin Zhang 001; et al. (ISSCC, 2006)

A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization. - Sriram R. Vangal; Yatin Vasant Hoskote; Nitin Borkar; Atila Alvandpour (IEEE J. Solid State Circuits, 2006)

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. - James W. Tschanz; Nam-Sung Kim; Saurabh Dighe; Jason Howard; Gregory Ruhl; Sriram R. Vangal; Siva G. Narendra; Yatin Hoskote; Howard Wilson; Carol Lam; Matthew Shuman; Carlos Tokunaga; et al. (ISSCC, 2007)

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS. - Sriram R. Vangal; Jason Howard; Gregory Ruhl; Saurabh Dighe; Howard Wilson; James W. Tschanz; David Finan; Priya Iyer; Arvind P. Singh; Tiju Jacob; Shailendra Jain; Sriram Venkataraman; et al. (ISSCC, 2007)

A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. - Muhammad M. Khellah; Dinesh Somasekhar; Yibin Ye; Nam-Sung Kim; Jason Howard; Gregory Ruhl; Murad Sunna; James W. Tschanz; Nitin Borkar; Fatih Hamzaoglu; Gunjan Pandya; Ali Farhang; et al. (IEEE J. Solid State Circuits, 2007)

A 5-GHz Mesh Interconnect for a Teraflops Processor. - Yatin Hoskote; Sriram R. Vangal; Arvind P. Singh; Nitin Borkar; Shekhar Borkar (IEEE Micro, 2007)

An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS. - Sriram R. Vangal; Jason Howard; Gregory Ruhl; Saurabh Dighe; Howard Wilson; James W. Tschanz; David Finan; Arvind P. Singh; Tiju Jacob; Shailendra Jain; Vasantha Erraguntla; Clark Roberts; et al. (IEEE J. Solid State Circuits, 2008)

Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. - Muhammad M. Khellah; Nam-Sung Kim; Yibin Ye; Dinesh Somasekhar; Tanay Karnik; Nitin Borkar; Gunjan Pandya; Fatih Hamzaoglu; Tom Coan; Yih Wang; Kevin Zhang 001; Clair Webb; et al. (IEEE J. Solid State Circuits, 2009)

Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. - Saurabh Dighe; Sriram R. Vangal; Paolo A. Aseron; Shasi Kumar; Tiju Jacob; Keith A. Bowman; Jason Howard; James W. Tschanz; Vasantha Erraguntla; Nitin Borkar; Vivek De; Shekhar Borkar (ISSCC, 2010)

A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. - Jason Howard; Saurabh Dighe; Yatin Vasant Hoskote; Sriram R. Vangal; David Finan; Gregory Ruhl; David Jenkins; Howard Wilson; Nitin Borkar; Gerhard Schrom; Fabric Pailet; Shailendra Jain; et al. (ISSCC, 2010)

The 48-core SCC Processor: the Programmer's View. - Timothy G. Mattson; Michael Riepen; Thomas Lehnig; Paul Brett; Werner Haas 002; Patrick Kennedy; Jason Howard; Sriram R. Vangal; Nitin Borkar; Gregory Ruhl; Saurabh Dighe (SC, 2010)

A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm. - Shailendra Jain; Vasantha Erraguntla; Sriram R. Vangal; Yatin Vasant Hoskote; Nitin Borkar; Tulasi Mandepudi; V. P. Karthik (VLSI Design, 2010)

Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. - Saurabh Dighe; Sriram R. Vangal; Paolo A. Aseron; Shasi Kumar; Tiju Jacob; Keith A. Bowman; Jason Howard; James W. Tschanz; Vasantha Erraguntla; Nitin Borkar; Vivek K. De; Shekhar Borkar (IEEE J. Solid State Circuits, 2011)

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. - Jason Howard; Saurabh Dighe; Sriram R. Vangal; Gregory Ruhl; Nitin Borkar; Shailendra Jain; Vasantha Erraguntla; Michael Konow; Michael Riepen; Matthias Gries; Guido Droege; Tor Lund-Larsen; et al. (IEEE J. Solid State Circuits, 2011)

A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS. - Praveen Salihundam; Shailendra Jain; Tiju Jacob; Shasi Kumar; Vasantha Erraguntla; Yatin Vasant Hoskote; Sriram R. Vangal; Gregory Ruhl; Nitin Borkar (IEEE J. Solid State Circuits, 2011)

An IA-32 processor with a wide voltage operating range in 32nm CMOS. - Gregory Ruhl; Saurabh Dighe; Shailendra Jain; Surhud Khare; Satish Yada; V. Ambili; Praveen Salihundam; Shiva Ramani; Sriram Muthukumar; M. Srinivasan; Arun Kumar; Shasi Kumar; et al. (Hot Chips Symposium, 2012)

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. - Shailendra Jain; Surhud Khare; Satish Yada; V. Ambili; Praveen Salihundam; Shiva Ramani; Sriram Muthukumar; M. Srinivasan; Arun Kumar; Shasi Kumar; Rajaraman Ramanarayanan; Vasantha Erraguntla; et al. (ISSCC, 2012)

A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip. - Praveen Salihundam; Mohammed Asadullah Khan; Shailendra Jain; Yatin Vasant Hoskote; Satish Yada; Shasi Kumar; Vasantha Erraguntla; Sriram R. Vangal; Nitin Borkar (VLSI Design, 2012)

Resiliency for many-core system on a chip. - Tanay Karnik; James W. Tschanz; Nitin Borkar; Jason Howard; Sriram R. Vangal; Vivek De; Shekhar Borkar (ASP-DAC, 2014)

System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators. - Ayan Paul; Sang Phill Park; Dinesh Somasekhar; Young Moon Kim; Nitin Borkar; Ulya R. Karpuzcu; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2016)