VLSI architecture and design for high performance adaptive video scaling. - Arun Raghupathy; Pohsiang Hsu; K. J. Ray Liu; Nitin Chandrachoodan (ISCAS (4), 1999)

An efficient timing model for hardware implementation of multirate dataflow graphs. - Nitin Chandrachoodan; Shuvra S. Bhattacharyya; K. J. Ray Liu (ICASSP, 2001)

Adaptive negative cycle detection in dynamic graphs. - Nitin Chandrachoodan; Shuvra S. Bhattacharyya; K. J. Ray Liu (ISCAS (5), 2001)

The hierarchical timing pair model. - Nitin Chandrachoodan; Shuvra S. Bhattacharyya; K. J. Ray Liu (ISCAS (5), 2001)

High-Level Synthesis of DSP Applications Using Adaptive Negative Cycle Detection. - Nitin Chandrachoodan; Shuvra S. Bhattacharyya; K. J. Ray Liu (EURASIP J. Adv. Signal Process., 2002)

Algorithm and VLSI architecture for high performance adaptive video scaling. - Arun Raghupathy; Nitin Chandrachoodan; K. J. Ray Liu (IEEE Trans. Multim., 2003)

The hierarchical timing pair model for multirate DSP applications. - Nitin Chandrachoodan; Shuvra S. Bhattacharyya; K. J. Ray Liu (IEEE Trans. Signal Process., 2004)

A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation. - Karthick Parashar; Nitin Chandrachoodan (FPL, 2007)

Rapid Abstract Control Model for Signal Processing Implementation. - Kannan Gaddam; Nitin Chandrachoodan; S. Srinivasan 001 (SiPS, 2007)

Efficient Implementation of IEEE Double Precision Floating-Point Multiplier on FPGA. - Manish Kumar Jaiswal; Nitin Chandrachoodan (ICIIS, 2008)

Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models. - Aman Kokrady; C. P. Ravikumar; Nitin Chandrachoodan (VLSI Design, 2008)

Efficient Implementation of Floating-Point Reciprocator on FPGA. - Manish Kumar Jaiswal; Nitin Chandrachoodan (VLSI Design, 2009)

Post-Synthesis Circuit Techniques for Runtime Leakage Reduction. - Seetal Potluri; Nitin Chandrachoodan; V. Kamakoti 001 (ISVLSI, 2011)

24th "IEEE International Conference on VLSI Design" Chennai, India, 2-7 January 2011. - Nitin Chandrachoodan; Shankar Balachandran (J. Low Power Electron., 2011)

A GPU implementation of belief propagation decoder for polar codes. - Bharath Kumar Reddy L.; Nitin Chandrachoodan (ACSCC, 2012)

GPU Implementation of a Programmable Turbo Decoder for Software Defined Radio Applications. - Dhiraj Reddy Nallapa Yoge; Nitin Chandrachoodan (VLSI Design, 2012)

Interconnect Aware Test Power Reduction. - Seetal Potluri; Nitin Chandrachoodan; V. Kamakoti 001 (J. Low Power Electron., 2012)

FPGA-Based High-Performance and Scalable Block LU Decomposition Architecture. - Manish Kumar Jaiswal; Nitin Chandrachoodan (IEEE Trans. Computers, 2012)

Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimization. - Vimitha A. Kuruvilla; Debjit Sinha; Jeff Piaget; Chandu Visweswariah; Nitin Chandrachoodan (DAC, 2013)

An inertial sensor-based system to develop motor capacity in children with cerebral palsy. - Shuo Qiao; Anil Prabhakar; Nitin Chandrachoodan; Namita Jacob; Harshvardhan Vathsangam (EMBC, 2013)

PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information. - Seetal Potluri; Satya Trinadh; Roopashree Baskaran; Nitin Chandrachoodan; V. Kamakoti 001 (ETS, 2013)

Scalable low power digital filter architectures for varying input dynamic range. - Sundarrajan Rangachari; Nitin Chandrachoodan (ISCAS, 2013)

Tutorial T1B: Riding the "Energy Consumption Horse" - from System-level Design to Silicon. - Prabhat Avasare; Nitin Chandrachoodan (VLSI Design, 2013)

Scalable Low Power FFT/IFFT Architecture with Dynamic Bit Width Configurability. - Sundarrajan Rangachari; Jaiganesh Balakrishnan; Nitin Chandrachoodan (VLSID, 2014)

iitRACE: A Memory Efficient Engine for Fast Incremental Timing Analysis and Clock Pessimism Removal. - Chaitanya Peddawad; Aman Goel; B. Dheeraj; Nitin Chandrachoodan (ICCAD, 2015)

Non-uniform DFT implementation for channel simulations in GPU. - Karthikeyan Natarajan; Nitin Chandrachoodan (NCC, 2015)

Designing a passive star optical network for the India-based Neutrino Observatory. - Vaibhav Pratap Singh; Nitin Chandrachoodan; Anil Prabhakar (NCC, 2015)

DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing. - Seetal Potluri; Satya Trinadh; Ch. Sobhan Babu; V. Kamakoti 001; Nitin Chandrachoodan (ACM Trans. Design Autom. Electr. Syst., 2015)

Guided multilevel approximation of less significant bits for power reduction. - D. Celia; Nitin Chandrachoodan (VDAT, 2016)

FFT/IFFT implementation using Vivado™ HLS. - Amit Salaskar; Nitin Chandrachoodan (VDAT, 2016)

A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips. - Gokulkrishnan Vadakkeveedu; V. Kamakoti 001; Nitin Chandrachoodan; Seetal Potluri (DFT, 2017)

FPGA Implementation of Non-Uniform DFT for Accelerating Wireless Channel Simulations (Abstract Only). - Srinivas Siripurapu; Aman Gayasen; Padmini Gopalakrishnan; Nitin Chandrachoodan (FPGA, 2017)

Scenario-Aware Dynamic Power Reduction Using Bias Addition. - Sundarrajan Rangachari; Jaiganesh Balakrishnan; Nitin Chandrachoodan (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Optimizing power-accuracy trade-off in approximate adders. - D. Celia; Vinita Vasudevan; Nitin Chandrachoodan (DATE, 2018)

Lossless Parallel Implementation of a Turbo Decoder on GPU. - Karthikeyan Natarajan; Nitin Chandrachoodan (HiPC, 2018)

Probabilistic Error Modeling for Two-part Segmented Approximate Adders. - D. Celia; Vinita Vasudevan; Nitin Chandrachoodan (ISCAS, 2018)

Data Subsetting: A Data-Centric Approach to Approximate Computing. - Younghoon Kim; Swagath Venkataramani; Nitin Chandrachoodan; Anand Raghunathan (DATE, 2019)

White Mirror: Leaking Sensitive Information from Interactive Netflix Movies using Encrypted Traffic Analysis. - Gargi Mitra; Prasanna Karthik Vairam; Patanjali SLPSK; Nitin Chandrachoodan; Kamakoti Veezhinathan (SIGCOMM Posters and Demos, 2019)

A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits. - Shivani Bathla; Rahul M. Rao; Nitin Chandrachoodan (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Depending on HTTP/2 for Privacy? Good Luck! - Gargi Mitra; Prasanna Karthik Vairam; Patanjali SLPSK; Nitin Chandrachoodan; Kamakoti Veezhinathan (DSN, 2020)

EASpiNN: Effective Automated Spiking Neural Network Evaluation on FPGA. - Sathish Panchapakesan; Zhenman Fang; Nitin Chandrachoodan (FCCM, 2020)

Energy Reduction in Turbo Decoding through Dynamically Varying Bit-Widths. - Sundarrajan Rangachari; Nitin Chandrachoodan (ISCAS, 2020)

Probabilistic spike propagation for FPGA implementation of spiking neural networks. - Abinand Nallathambi; Nitin Chandrachoodan (CoRR, 2020)

Scalable pseudo-exhaustive methodology for testing and diagnosis in flow-based microfluidic biochips. - Gokulkrishnan Vadakkeveedu; Kamakoti Veezhinathan; Nitin Chandrachoodan; Seetal Potluri (IET Comput. Digit. Tech., 2020)

Analysis of power-accuracy trade-off in digital signal processing applications using low-power approximate adders. - Celia Dharmaraj; Vinita Vasudevan; Nitin Chandrachoodan (IET Comput. Digit. Tech., 2021)

A Smoothed LASSO-Based DNN Sparsification Technique. - Basava Naga Girish Koneru; Nitin Chandrachoodan; Vinita Vasudevan (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Optimization of Signal Processing Applications Using Parameterized Error Models for Approximate Adders. - Celia Dharmaraj; Vinita Vasudevan; Nitin Chandrachoodan (ACM Trans. Embed. Comput. Syst., 2021)

Split-Knit Convolution: Enabling Dense Evaluation of Transpose and Dilated Convolutions on GPUs. - Arjun Menon Vadakkeveedu; Debabrata Mandal; Pradeep Ramachandran; Nitin Chandrachoodan (HIPC, 2022)

Layerwise Disaggregated Evaluation of Spiking Neural Networks. - Abinand Nallathambi; Sanchari Sen; Anand Raghunathan; Nitin Chandrachoodan (ISLPED, 2022)

Reduced Memory Viterbi Decoding for Hardware-accelerated Speech Recognition. - Pani Prithvi Raj; Akhil Reddy Pakala; Nitin Chandrachoodan (ACM Trans. Embed. Comput. Syst., 2022)

Work-in-Progress: QRCNN: Scalable CNNs. - Dara Nagaraju; Nitin Chandrachoodan (CASES, 2023)

ViTA: A Vision Transformer Inference Accelerator for Edge Applications. - Shashank Nag; Gourav Datta; Souvik Kundu 002; Nitin Chandrachoodan; Peter A. Beerel (ISCAS, 2023)

Compressing fully connected layers of deep neural networks using permuted features. - Dara Nagaraju; Nitin Chandrachoodan (IET Comput. Digit. Tech., 2023)

Slimmer CNNs Through Feature Approximation and Kernel Size Reduction. - Dara Nagaraju; Nitin Chandrachoodan (IEEE Open J. Circuits Syst., 2023)

Snoopy: A Webpage Fingerprinting Framework With Finite Query Model for Mass-Surveillance. - Gargi Mitra; Prasanna Karthik Vairam; Sandip Saha; Nitin Chandrachoodan; V. Kamakoti 001 (IEEE Trans. Dependable Secur. Comput., 2023)

AlphaZip: Neural Network-Enhanced Lossless Text Compression. - Swathi Shree Narashiman; Nitin Chandrachoodan (CoRR, 2024)

Effective Memory Management and Sparse Aware Cache for Row-Wise Sparse CNNs. - MC Balasubramaniam; Basava Naga Girish Koneru; Nitin Chandrachoodan (VLSID, 2025)

Hardware Implementation of Blind Decoding of Downlink Control Information for 5G. - Y. Anu rajarajeswari; Nitin Chandrachoodan; Anji Babu Vadapalli; J. Klutto Milleth (VLSID, 2025)