New reliability mechanisms in memory design for sub-22nm technologies. - Nivard Aymerich; A. Asenov; Andrew R. Brown; Ramon Canal; Binjie Cheng; Joan Figueras; Antonio González 001; Enric Herrero; S. Markov; Miguel Miranda; Peyman Pouyan; Tanausú Ramírez; et al. (IOLTS, 2011)

Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells. - Nivard Aymerich; Shrikanth Ganapathy; Antonio Rubio 001; Ramon Canal; Antonio González 001 (Integr., 2012)

Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy. - Nivard Aymerich; Antonio Rubio 001 (Microprocess. Microsystems, 2012)

Variability robustness enhancement for 7nm FinFET 3T1D-DRAM cells. - Esteve Amat; Carmen G. Almudéver; Nivard Aymerich; Antonio Rubio 001; Ramon Canal (MWSCAS, 2013)

Extending the fundamental error bounds for asymmetric error reliable computation. - Nivard Aymerich; Antonio Rubio 001 (NANOARCH, 2013)

Systematic and random variability analysis of two different 6T-SRAM layout topologies. - Esteve Amat; E. Amatllé; Sergio Gómez; Nivard Aymerich; Carmen G. Almudéver; Francesc Moll; Antonio Rubio 001 (Microelectron. J., 2013)

Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm. - Esteve Amat; Carmen G. Almudéver; Nivard Aymerich; Ramon Canal; Antonio Rubio 001 (Microelectron. J., 2014)

Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip. - David R. Ditzel; Roger Espasa; Nivard Aymerich; Allen Baum; Tom Berg; Jim Burr; Eric Hao; Jayesh Iyer; Miquel Izquierdo; Shankar Jayaratnam; Darren Jones; Chris Klingner; et al. (HCS, 2021)