Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed on 576 digital neurons. - Moritoshi Yasunaga; Noboru Masuda; Masayoshi Yagyu; Mitsuo Asai; Minoru Yamada; Akira Masaki (IJCNN, 1990)

A Novel Clock Distribution System for CMOS VLSI. - Kenichi Ishibashi; Takehisa Hayashi; Toshio Doi; Noboru Masuda; Akira Yamagiwa; Toshihiro Okabe (ICCD, 1993)

A self-learning digital neural network using wafer-scale LSI. - Moritoshi Yasunaga; Noboru Masuda; Masayoshi Yagyu; Mitsuo Asai; Katsunari Shibata; Mitsuo Ooyama; Minoru Yamada; Takahiro Sakaguchi; Masashi Hashimoto (IEEE J. Solid State Circuits, 1993)

Impedance Measurement and Analysis of Water-Containing Foodstuffs in Refrigeration Process. - Hideo Kusano; Teruo Negishi; Noboru Masuda (J. Robotics Mechatronics, 1994)

A Study of a Stable Driving Circuit for Arbitrary-Shaped Electroluminescent Elements. - Yasuyuki Kitada; Noboru Masuda; Hiroshi Nakane; Sadao Yamazaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process. - Koji Fukuda; Hiroki Yamashita; Goichi Ono; Ryo Nemoto; Eiichi Suzuki; Noboru Masuda; Takashi Takemoto; Fumio Yuki; Tatsuya Saito (IEEE J. Solid State Circuits, 2010)

10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link. - Goichi Ono; Keiki Watanabe; Takashi Muto; Hiroki Yamashita; Koji Fukuda; Noboru Masuda; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Fumio Yuki; Masayoshi Yagyu; Hidehiro Toyoda; et al. (ISSCC, 2011)

A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link. - Goichi Ono; Keiki Watanabe; Takashi Muto; Hiroki Yamashita; Koji Fukuda; Noboru Masuda; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Fumio Yuki; Masayoshi Yagyu; Hidehiro Toyoda; et al. (IEEE J. Solid State Circuits, 2011)

A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS. - Takashi Takemoto; Hiroki Yamashita; Takehito Kamimura; Fumio Yuki; Noboru Masuda; Hidehiro Toyoda; Norio Chujo; Kenji Kogo; Yong Lee; Shinji Tsuji; Shinji Nishimura (VLSIC, 2012)

A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion. - Takashi Takemoto; Hiroki Yamashita; Fumio Yuki; Noboru Masuda; Hidehiro Toyoda; Norio Chujo; Yong Lee; Shinji Tsuji; Shinji Nishimura (IEEE J. Solid State Circuits, 2014)