Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode. - Takeshi Honda; Noboru Sakimura; Tadahiko Sugibayashi; Naoki Kasai; Hiromitsu Hada; Shuichi Tahara (IEICE Trans. Electron., 2007)

MRAM Applications Using Unlimited Write Endurance. - Tadahiko Sugibayashi; Takeshi Honda; Noboru Sakimura; Shuichi Tahara; Naoki Kasai (IEICE Trans. Electron., 2007)

MRAM Cell Technology for Over 500-MHz SoC. - Noboru Sakimura; Tadahiko Sugibayashi; Takeshi Honda; Hiroaki Honjo; Shinsaku Saito; Tetsuhiro Suzuki; Nobuyuki Ishiwata; Shuichi Tahara (IEEE J. Solid State Circuits, 2007)

A 16-Mb Toggle MRAM With Burst Modes. - Tadahiko Sugibayashi; Noboru Sakimura; Takeshi Honda; Kiyokazu Nagahara; Kiyotaka Tsuji; Hideaki Numata; Sadahiko Miura; Ken-ichi Shimura; Yuko Kato; Shinsaku Saito; Yoshiyuki Fukumoto; Hiroaki Honjo; et al. (IEEE J. Solid State Circuits, 2007)

A 90nm 12ns 32Mb 2T1MTJ MRAM. - Ryusuke Nebashi; Noboru Sakimura; Hiroaki Honjo; Shinsaku Saito; Yuichi Ito; Sadahiko Miura; Yuko Kato; Kaoru Mori; Yasuaki Ozaki; Yosuke Kobayashi; Norikazu Ohshima; Keizo Kinoshita; et al. (ISSCC, 2009)

Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros. - Ryusuke Nebashi; Noboru Sakimura; Tadahiko Sugibayashi; Naoki Kasai (IEICE Trans. Electron., 2009)

Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs. - Noboru Sakimura; Tadahiko Sugibayashi; Ryusuke Nebashi; Naoki Kasai (IEEE J. Solid State Circuits, 2009)

Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS. - Makoto Miyamura; Shogo Nakaya; Munehiro Tada; Toshitsugu Sakamoto; Koichiro Okamoto; Naoki Banno; Shinji Ishida; Kimihiko Ito; Hiromitsu Hada; Noboru Sakimura; Tadahiko Sugibayashi; Masato Motomura (ISSCC, 2011)

High-speed simulator including accurate MTJ models for spintronics integrated circuit design. - Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Hiroaki Honjo; Tadahiko Sugibayashi; Hiroki Koike; Takashi Ohsawa; Shunsuke Fukami; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (ISCAS, 2012)

MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI. - Masanori Natsui; Takahiro Hanyu; Noboru Sakimura; Tadahiko Sugibayashi (ISCAS, 2013)

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. - Masanori Natsui; Daisuke Suzuki; Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Ayuka Morioka; Tadahiko Sugibayashi; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; et al. (ISSCC, 2013)

A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes. - Shogo Nakaya; Makoto Miyamura; Noboru Sakimura; Yuichi Nakamura 002; Tadahiko Sugibayashi (IPSJ Trans. Syst. LSI Des. Methodol., 2013)

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. - Ryusuke Nebashi; Noboru Sakimura; Hiroaki Honjo; Ayuka Morioka; Yukihide Tsuji; Kunihiko Ishihara; Keiichi Tokutome; Sadahiko Miura; Shunsuke Fukami; Keizo Kinoshita; Takahiro Hanyu; Tetsuo Endoh; et al. (ISCAS, 2014)

Soft-Delay-Error Evaluation in Content-Addressable Memory. - Naoya Onizawa; Shoun Matsunaga; Noboru Sakimura; Ryusuke Nebashi; Tadahiko Sugibayashi; Takahiro Hanyu (ISMVL, 2014)

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications. - Noboru Sakimura; Yukihide Tsuji; Ryusuke Nebashi; Hiroaki Honjo; Ayuka Morioka; Kunihiko Ishihara; Keizo Kinoshita; Shunsuke Fukami; Sadahiko Miura; Naoki Kasai; Tetsuo Endoh; Hideo Ohno; et al. (ISSCC, 2014)

A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture. - Hooman Jarollahi; Naoya Onizawa; Vincent Gripon; Noboru Sakimura; Tadahiko Sugibayashi; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu; Warren J. Gross (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme. - Shoun Matsunaga; Akira Mochizuki; Noboru Sakimura; Ryusuke Nebashi; Tadahiko Sugibayashi; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (IEICE Electron. Express, 2014)

A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. - Daisuke Suzuki; Noboru Sakimura; Masanori Natsui; Akira Mochizuki; Tadahiko Sugibayashi; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (IEICE Electron. Express, 2014)

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. - Masanori Natsui; Daisuke Suzuki; Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Ayuka Morioka; Tadahiko Sugibayashi; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; et al. (IEEE J. Solid State Circuits, 2015)

Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory. - Naoya Onizawa; Noboru Sakimura; Ryusuke Nebashi; Tadahiko Sugibayashi; Takahiro Hanyu (J. Multiple Valued Log. Soft Comput., 2016)